Configurable, High Throughput, Irregular LDPC Decoder Architecture: Tradeoff Analysis and Implementation
Cavallaro, Joseph R.
FPGA Implementation; LDPC decoder; Flexible Architecture
With the current trend of the increase in the data-rate requirements of wireless systems, there will be a huge need to increase their performance by utilizing more sophisticated channel coding algorithms. Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable these future wireless systems to grow with the demand. This paper presents a novel flexible architecture for irregular LDPC decoder that supports twelve combinations of code lengths - 648, 1296, 1944 bits - and code rates- 1/2, 2/3, 3/4, 5/6 - based on the IEEE 802.11n standard. All the codes correspond to a block-structured parity check matrix, in which the sub-blocks are either a shifted identity matrix or a zero matrix. A prototype of the LDPC decoder has been implemented and tested on a Xilinx FPGA and has been synthesized for ASIC.
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- ECE Publications