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dc.contributor.authorKarkooti, Marjan
Cavallaro, Joseph R.
Dick, Chris
dc.creatorKarkooti, Marjan
Cavallaro, Joseph R.
Dick, Chris 2007-10-31T00:49:04Z 2007-10-31T00:49:04Z 2005-11-01 2005-11-01
dc.identifier.citation M. Karkooti, J. R. Cavallaro and C. Dick, "FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm," 2005.
dc.description Conference Paper
dc.description.abstract This paper presents a novel architecture for matrix inversion by generalizing the QR decomposition-based recursive least square (RLS) algorithm. The use of Squared Givens rotations and a folded systolic array makes this architecture very suitable for FPGA implementation. Input is a 4 by 4 matrix of complex, floating point values. The matrix inversion design can achieve throughput of 0.13 M updates per second on a state of the art Xilinx Virtex4 FPGA running at 115 MHz. Due to the modular partitioning and interfacing between multiple Boundary and Internal processing units, this architecture is easily extendable for other matrix sizes.
dc.language.iso eng
Matrix inversion
dc.title FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm
dc.type Conference paper 2006-03-08
dc.citation.bibtexName inproceedings 2006-03-08
dc.contributor.orgCenter for Multimedia Communications (
Matrix inversion
dc.citation.conferenceName Asilomar Conference on Signals, Systems, and Computers
dc.type.dcmi Text
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  • ECE Publications [1474]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • Rice Wireless [268]
    Publications by Rice Faculty and graduate students in the Rice Wireless group

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