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    FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm

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    Author
    Karkooti, Marjan; Cavallaro, Joseph R.; Dick, Chris
    Date
    2006-03-08
    Abstract
    This paper presents a novel architecture for matrix inversion by generalizing the QR decomposition-based recursive least square (RLS) algorithm. The use of Squared Givens rotations and a folded systolic array makes this architecture very suitable for FPGA implementation. Input is a 4 by 4 matrix of complex, floating point values. The matrix inversion design can achieve throughput of 0.13 M updates per second on a state of the art Xilinx Virtex4 FPGA running at 115 MHz. Due to the modular partitioning and interfacing between multiple Boundary and Internal processing units, this architecture is easily extendable for other matrix sizes.
    Description
    Conference Paper
    Citation
    M. Karkooti, J. R. Cavallaro and C. Dick, "FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm," 2005.
    Published Version
    http://dx.doi.org/10.1109/ACSSC.2005.1600043
    Keyword
    FPGA; Matrix inversion; FPGA; Matrix inversion
    Type
    Conference paper
    Citable link to this page
    https://hdl.handle.net/1911/20001
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    • ECE Publications [1468]
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    Managed by the Digital Scholarship Services at Fondren Library, Rice University
    Physical Address: 6100 Main Street, Houston, Texas 77005
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    Site Map