FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm
Author
Karkooti, Marjan; Cavallaro, Joseph R.; Dick, Chris
Date
2006-03-08Abstract
This paper presents a novel architecture for matrix
inversion by generalizing the QR decomposition-based recursive
least square (RLS) algorithm. The use of Squared Givens
rotations and a folded systolic array makes this architecture very
suitable for FPGA implementation. Input is a 4 by 4 matrix of
complex, floating point values. The matrix inversion design can
achieve throughput of 0.13 M updates per second on a state
of the art Xilinx Virtex4 FPGA running at 115 MHz. Due
to the modular partitioning and interfacing between multiple
Boundary and Internal processing units, this architecture is easily
extendable for other matrix sizes.
Description
Conference Paper
Citation
Published Version
Keyword
FPGA; Matrix inversion; FPGA; Matrix inversion
Type
Conference paper
Citable link to this page
https://hdl.handle.net/1911/20001Metadata
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