Semi-Parallel Architectures For Real-time LDPC Coding
Reconfigurable architecture; FPGA implementation; channel coding; parallel architecture; area-time tradeoffs.
Error correcting codes (ECC) enable the communication systems to have a low-power, reliable transmission over noisy channels. ow Density Parity Check codes are the best known ECC code that can achieve data rates very close to Shannon limit. This thesis presents a semi-parallel architecture for decoding Low Density Parity Check (LDPC) codes. A modified version of Min-Sum algorithm has been used for the decoder, which has the advantage of simpler computations compared to Sum-Product algorithm without any loss in performance. To balance the area-time trade-off of the design, a special structure is proposed for the parity-check matrix. An efficient semi-parallel decoder for a family of (3,6) LDPC codes has been implemented in VHDL for programmable hardware. Simulation results show that our proposed decoder for a block length of 1536 bits can achieve data rates up to 127 Mbps. The design is scalable and reconfigurable for different block sizes.