Semi-parallel Reconfigurable Architectures for Real-time LDPC Decoding
Cavallaro, Joseph R.
Reconfigurable architecture; FPGA implementation; Channel coding; Parallel architecture; Area-time tradeoffs
This paper presents a semi-parallel architecture for decoding Low Density Parity Check (LDPC) codes. A modified version of Min-Sum algorithm has been used which has the advantage of simpler computations compared to Sum-Product algorithm without any loss in performance. Special structure of the parity check matrix of the proposed code leads to an efficient semi-parallel implementation of the decoder for a family of (3,6) LDPC codes. A prototype architecture has been implemented in VHDL on programmable hardware. The design is easily scalable and reconfigurable for larger block sizes. Simulation results show that our proposed decoder for a block length of 1536 bits can achieve data rates up to 127 Mbps.
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- ECE Publications