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    Hermitian Optimization and Scalable VLSI Architecture for Circulant Approximated MIMO Equalizer in CDMA Downlink

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    Author
    Guo, Yuanbin; McCain, Dennis; Cavallaro, Joseph R.
    Date
    2005-06-24
    Abstract
    In this paper, we propose a parallel and pipelined VLSI architecture for a circulant approximated equalizer for the MIMOCDMA systems. The FFT-based tap solver reduces the Direct-Matrix-Inverse of the size (NF x NF) to the inverse of O(N) sub-matrices of the size (N x N). Hermitian optimization and tree pruning is proposed to reduce the number and complexity of the FFTs. A divide-andconquer method partitions the 4£4 sub-matrices into 2x2 sub-matrices and simplifies the inverse of sub-matrices. Generic VLSI architecture is derived to eliminate the redundancies in the complex operations. Multiple level parallelism and pipelining is investigated with a Catapult C High-Level-Synthesis (HLS) methodology. This leads to efficient VLSI architectures with 3x further complexity reduction. The scalable VLSI architectures are prototyped with the Xilinx FPGAs and achieve area/time efficiency.
    Description
    Conference Paper
    Citation
    Y. Guo, D. McCain and J. R. Cavallaro, "Hermitian Optimization and Scalable VLSI Architecture for Circulant Approximated MIMO Equalizer in CDMA Downlink," 2005.
    Published Version
    http://dx.doi.org/10.1109/VETECF.2005.1558489
    Keyword
    MIMO; CDMA; chip equalizer; Hermitian optimization; MIMO; More... CDMA; chip equalizer; Hermitian optimization Less...
    Type
    Conference paper
    Citable link to this page
    https://hdl.handle.net/1911/19940
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    • ECE Publications [1468]
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    Managed by the Digital Scholarship Services at Fondren Library, Rice University
    Physical Address: 6100 Main Street, Houston, Texas 77005
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    Site Map