Rice Univesrity Logo
    • FAQ
    • Deposit your work
    • Login
    View Item 
    •   Rice Scholarship Home
    • Faculty & Staff Research
    • George R. Brown School of Engineering
    • Electrical and Computer Engineering
    • ECE Publications
    • View Item
    •   Rice Scholarship Home
    • Faculty & Staff Research
    • George R. Brown School of Engineering
    • Electrical and Computer Engineering
    • ECE Publications
    • View Item
    JavaScript is disabled for your browser. Some features of this site may not work without it.

    A low complexity and low power SoC design architecture for adaptive MAI suppression in CDMA systems

    Thumbnail
    Name:
    Guo2005May1Alowcomple.PDF
    Size:
    390.0Kb
    Format:
    PDF
    View/Open
    Author
    Guo, Yuanbin; Cavallaro, Joseph R.
    Date
    2005-05-01
    Abstract
    In this paper, we propose a reduced complexity and power efficient System-on-Chip (SoC) architecture for adaptive interference suppression in CDMA systems. The adaptive Parallel-Residue-Compensation architecture leads to significant performance gain over the conventional interference cancellation algorithms. The multi-code commonality is explored to avoid the direct Interference Cancellation (IC), which reduces the IC complexity from O(K^2N) to O(KN). The physical meaning of the complete versus weighted IC is applied to clip the weights above a certain threshold so as to reduce the VLSI circuit activity rate. Novel scalable SoC architectures based on simple combinational logic are proposed to eliminate dedicated multipliers with at least 10X saving in hardware resource. A Catapult C High Level Synthesis methodology is apply to explore the VLSI design space extensively and achieve at least 4£ speedup. Multi-stage Convergence-Masking-Vector combined with clock gating is proposed to reduce the VLSI dynamic power consumption by up to 90%.
    Description
    Journal Paper
    Citation
    Y. Guo and J. R. Cavallaro, "A low complexity and low power SoC design architecture for adaptive MAI suppression in CDMA systems," Journal of VLSI Signal Processing, 2005.
    Published Version
    http://dx.doi.org/10.1007/s11265-006-8535-9
    Keyword
    Interference cancellation; low power; CDMA; adaptive; SoC; More... VLSI.; Interference cancellation; low power; CDMA; adaptive; SoC; VLSI. Less...
    Type
    Journal article
    Citable link to this page
    https://hdl.handle.net/1911/19936
    Metadata
    Show full item record
    Collections
    • ECE Publications [1468]
    • Rice Wireless [268]

    Home | FAQ | Contact Us | Privacy Notice | Accessibility Statement
    Managed by the Digital Scholarship Services at Fondren Library, Rice University
    Physical Address: 6100 Main Street, Houston, Texas 77005
    Mailing Address: MS-44, P.O.BOX 1892, Houston, Texas 77251-1892
    Site Map

     

    Searching scope

    Browse

    Entire ArchiveCommunities & CollectionsBy Issue DateAuthorsTitlesSubjectsTypeThis CollectionBy Issue DateAuthorsTitlesSubjectsType

    My Account

    Login

    Statistics

    View Usage Statistics

    Home | FAQ | Contact Us | Privacy Notice | Accessibility Statement
    Managed by the Digital Scholarship Services at Fondren Library, Rice University
    Physical Address: 6100 Main Street, Houston, Texas 77005
    Mailing Address: MS-44, P.O.BOX 1892, Houston, Texas 77251-1892
    Site Map