FFT-Accelerated Iterative MIMO Chip Equalizer Architecture For CDMA Downlink
Cavallaro, Joseph R.
MIMO; chip equalizer; CDMA; iterative
In this paper, we present a novel FFT-accelerated iterative Linear MMSE chip equalizer in the MIMO CDMA downlink receiver. The reversed form time-domain matrix multiplication in the Conjugate Gradient iteration is accelerated by an equivalent frequency-domain circular convolution with FFT-based "overlap-save" architecture. The iteration rapidly refines a crude initial approximation to the actual final equalizer taps. This avoids the Direct-Matrix-Inverse with O((<i>NL</i>)³) complexity, and reduces the standard CG complexity from O((<i>NL</i>)²) to O(<i>NL</i>log<sub>2</sub>(<i>NL</i>)). Simulation demonstrates strong numerical stability and promising performance/complexity tradeoff, especially for very long channels.