Reducing Dynamic Power Consumption in Next Generation DS-CDMA Mobile Communication Receivers
Cavallaro, Joseph R.
Low-Power; Rake Receiver; FPGA Implementation; Fixed-Point Arithmetic
Reduction of the power consumption in portable wireless receivers is an important consideration for next-generation cellular systems speciﬁed by standards such as the UMTS, IMT2000. This paper explores the architectural design-space and methodologies for reducing the dynamic power dissipation in the Direct Sequence Code Division Multiple Access (DS-CDMA) downlink RAKE receiver. Starting with a reference implementation of the DS-CDMA RAKE receiver, we demonstrate design methodologies for achieving signiﬁcant power reduction, while highlighting the corresponding performance trade-offs. At the algorithm level, we investigate the tradeoffs of reduced precision and arithmetic complexity on the receiver performance. We then present two architectures for implementing the reference and reduced complexity receivers, and analyze these architectures with respect to their dynamic power dissipation. Our ﬁndings report that reduction in precision from a 16 bit to a 10 bit data-path is found to yield signiﬁcant power savings of 25.6% in the reference RAKE receiver architecture, with a performance loss of less than 1 dB. Further, a power reduction of upto 24.65% is achieved in a 16 bit data-path for the reduced complexity RAKE receiver compared to the reference architecture, with a performance loss of less than 2 dB. Although there is a tradeoff in performance, adaptive power saving is very important for mobile wireless terminals. The combined effect of reduced precision and complexity reduction leads to a 37.44% savings in baseband processing power.