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dc.contributor.authorChadha, Kanu
Cavallaro, Joseph R.
dc.creatorChadha, Kanu
Cavallaro, Joseph R.
dc.date.accessioned 2007-10-31T00:38:33Z
dc.date.available 2007-10-31T00:38:33Z
dc.date.issued 2001-11-20
dc.date.submitted 2001-11-20
dc.identifier.citation K. Chadha and J. R. Cavallaro, "A reconfigurable viterbi decoder architecture," vol. 1, 2001.
dc.identifier.urihttps://hdl.handle.net/1911/19764
dc.description Conference Paper
dc.description.abstract We present the design and implementation of a novel reconfigurable Viterbi decoder which provides dynamic adaptation to different constraint length and code rate convolutional codes. A decoder what supports constraint lengths from 3-7, and code rates ½-1/3 has been synthesized on an FPGA. With a throughput of 20 Mbps, the proposed decoder is suitable for use in receiver architectures of the 802.11a wireless local area network and 3G cellular code division multiple access environments. Results show that the area overhead associated with such a reconfigurable implementation as compared to a fixed constraint length 7 implementation is just 2.9%.
dc.description.sponsorship Texas Advanced Technology Program
dc.description.sponsorship Nokia
dc.description.sponsorship National Science Foundation
dc.language.iso eng
dc.subjectviterbi decoder architecture
dc.title A reconfigurable viterbi decoder architecture
dc.type Conference paper
dc.date.note 2002-04-17
dc.citation.bibtexName inproceedings
dc.date.modified 2003-11-09
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)
dc.subject.keywordviterbi decoder architecture
dc.citation.volumeNumber 1
dc.citation.conferenceName Asilomar Conference on Signals, Systems, and Computers
dc.type.dcmi Text
dc.type.dcmi Text
dc.identifier.doihttp://dx.doi.org/10.1109/ACSSC.2001.986882
dc.citation.firstpage 66
dc.citation.lastpage 71


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  • ECE Publications [1450]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students

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