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dc.contributor.authorCavallaro, Joseph R.
Radosavljevic, Predrag
dc.creatorCavallaro, Joseph R.
Radosavljevic, Predrag
dc.date.accessioned 2007-10-31T00:38:29Z
dc.date.available 2007-10-31T00:38:29Z
dc.date.issued 2004-06-01
dc.date.submitted 2004-06-01
dc.identifier.urihttps://hdl.handle.net/1911/19762
dc.description Conference paper
dc.description.abstract Efficiency and flexibility are crucial features of the processors in the next generation of wireless cellular systems. Processors need to be efficient in order to satisfy real-time requirements for very demanding algorithms in new emerging wireless standards (3GPP, 4G, 802.11x, WiFi, DVD-S2, DAB, just to name a few). Flexibility, on the other hand, allows design modifications to respond to the evolution of standards (from GPRS to 3G, for example), worldwide compatibility (UMTS in Europe and Asia, CDMA2000 in North America), changes of user requirements depending of the quality of service (QoS), etc. Often, efficiency and flexibility goals are conflicting. Efficiency is related to the more custom hardware implementation such as ASIC processors. On the other hand, flexibility is the basic feature of programmable platforms such as DSP processors. While computationally efficient and low power solutions, ASIC processors for wireless applications are often not flexible enough to support necessary variations of implemented algorithms. ASIC design, especially in deep sub micron technologies, is very complex task and the manufacturing costs are also high. It is cheaper to write and debug software (application written in high level languages) than directly design, debug and manufacture hardware. Furthermore, there are increasing demands for products with low time-to-market, which is not primary characteristic of the ASIC design. On the other hand, DSP processor, although fully programmable, cannot achieve high performance with low power dissipation. DSP cores are often not able to achieve high level of instruction and data parallelism required for future generations of wireless systems.
dc.description.sponsorship Nokia
dc.description.sponsorship Nokia/Texas Instruments
dc.language.iso eng
dc.subjectASIP
3GPP
ASIC
DSP
Flexibility
Customization
Retargetable Compiler
Hardware Design Flow
dc.title ASIP Architecture for Future Wireless Systems: Flexibility and Customization
dc.type Conference paper
dc.date.note 2004-05-14
dc.citation.bibtexName inproceedings
dc.date.modified 2004-08-30
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)
dc.subject.keywordASIP
3GPP
ASIC
DSP
Flexibility
Customization
Retargetable Compiler
Hardware Design Flow
dc.citation.conferenceName Wireless World Research Forum (WWRF)
dc.type.dcmi Text
dc.type.dcmi Text
dc.identifier.citation J. R. Cavallaro and P. Radosavljevic, "ASIP Architecture for Future Wireless Systems: Flexibility and Customization," 2004.


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  • DSP Publications [508]
    Publications by Rice Faculty and graduate students in digital signal processing.
  • ECE Publications [1456]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students

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