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CORDIC Arithmetic for an SVD Processor

dc.contributor.authorCavallaro, Joseph R.
Luk, Franklin T.
dc.creatorCavallaro, Joseph R.
Luk, Franklin T.
dc.date.accessioned 2007-10-31T00:38:18Z
dc.date.available 2007-10-31T00:38:18Z
dc.date.issued 1988-06-20
dc.date.submitted 2001-08-31
dc.identifier.citation J. R. Cavallaro and F. T. Luk, "CORDIC Arithmetic for an SVD Processor," Journal of Parallel and Distributed Computing, vol. 5, no. 3, 1988.
dc.identifier.urihttps://hdl.handle.net/1911/19758
dc.description Journal Paper
dc.description.abstract Arithmetic issues in the calculation of the Singular Value Decomposition (SVD) are discussed. Traditional algorithms using hardware division and square root are replaced with the special purpose CORDIC algorithms for computing vector rotations and inverse tangents. The CORDIC 2 x 2 SVD processor can be twice as fast as one assembled from traditional hardware units. A prototype VLSI implementation of a CORDIC SVD processor array is planned for use in real-time signal processing applications.
dc.language.iso eng
dc.subjectSingular Value Decomposition (SVD)
CORDIC algorithms
VLSI
dc.title CORDIC Arithmetic for an SVD Processor
dc.type Journal article
dc.citation.bibtexName article
dc.citation.journalTitle Journal of Parallel and Distributed Computing
dc.date.modified 2003-11-04
dc.contributor.orgCenter for Multimedia Communications (http://cmc.rice.edu/)
dc.subject.keywordSingular Value Decomposition (SVD)
CORDIC algorithms
VLSI
dc.citation.volumeNumber 5
dc.citation.issueNumber 3
dc.type.dcmi Text
dc.type.dcmi Text
dc.identifier.doihttp://dx.doi.org/10.1109/ARITH.1987.6158686
dc.citation.firstpage 271
dc.citation.lastpage 290


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  • ECE Publications [1473]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • Rice Wireless [268]
    Publications by Rice Faculty and graduate students in the Rice Wireless group

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