VLSI Implementation of a CORDIC SVD Processor

Files in this item

Files Size Format View
Cav1989Jun5VLSIImplem.PDF 442.0Kb application/pdf Thumbnail

Show full item record

Item Metadata

Title: VLSI Implementation of a CORDIC SVD Processor
Author: Cavallaro, Joseph R.; Keleher, Michael P.; Price, Russell H.; Thomas, Gregory S.
Type: Conference paper
xmlui.Rice_ECE.Keywords: CORDIC; SVD; VLSI; implementation; processor
Citation: J. R. Cavallaro, M. P. Keleher, R. H. Price and G. S. Thomas, "VLSI Implementation of a CORDIC SVD Processor," pp. 256-260, 1991.
Abstract: The design and custom CMOS VLSI implementation of a CORDIC SVD processor is presented. Special-purpose parallel processor arrays have many important applications in real-time signal processing. The processor architecture is reviewed and the current CORDIC Z Control and X,Y Data Path chips are described. The hierarchiacal design methodology ill lead next to a full CORDIC SVD processor and array.
Date Published: 1991-06-20

This item appears in the following Collection(s)

  • ECE Publications [1054 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students