Electrical and thermal modeling of electrostatic discharge protection structures for submicron VLSI

Abstract

A modeling technique has been developed which simulates a semiconductor device subjected to electrostatic discharge (ESD) stress according to the human body model (HBM). To accomplish this, a computer program was developed which solves the electron and hole continuity equations, Poisson's equation, and the heat flow equation in one dimension. The program has been applied to npn structures typical of the parasitic bipolar devices found in MOS output stages. Profiles from lightly-doped drain (LDD), double-diffused drain (DDD), and graded drain (GD) device structures were investigated. The performance of these various profiles under ESD stress has been compared in order to understand their functioning and to determine the important design parameters. It is found that device heating is reduced for structures in which the doping profile rises steeply to a high concentration in the drain region near the metallurgical junction. The rate of heating is related to reduced carrier saturation velocity due to local heating and its effects on charge distribution, electric field, and total potential drop across the reverse-biased junction. The modeling technique presented gives results which are in reasonable agreement with measured data. This technique should be a useful tool for evaluating new device structures, fabrication processes, or process changes before committing to the costly and time-consuming process of actual device fabrication.