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    Semi-parallel architectures for real-time LDPC coding

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    Author
    Karkooti, Marjan
    Date
    2004
    Advisor
    Cavallaro, Joseph R.
    Degree
    Master of Science
    Abstract
    Error correcting codes (ECC) enable the communication systems to have a low-power, reliable transmission over noisy channels. Low Density Parity Check codes are the best known ECC code that can achieve data rates very close to Shannon limit. This thesis presents a semi-parallel architecture for decoding Low Density Parity Check (LDPC) codes. A modified version of Min-Sum algorithm has been used for the decoder, which has the advantage of simpler computations compared to Sum-Product algorithm without any loss in performance. To balance the area time trade-off of the design, a special structure is proposed for the parity-check matrix. An efficient semi-parallel decoder for a family of (3, 6) LDPC codes has been implemented in VHDL for programmable hardware. Simulation results show that our proposed decoder for a block length of 1536 bits can achieve data rates up to 127 Mbps. The design is scalable and reconfigurable for different block sizes.
    Keyword
    Electronics; Electrical engineering
    Citation
    Karkooti, Marjan. "Semi-parallel architectures for real-time LDPC coding." (2004) Master’s Thesis, Rice University. http://hdl.handle.net/1911/17694.
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    • ECE Theses and Dissertations [597]
    • Rice University Electronic Theses and Dissertations [12052]

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    Managed by the Digital Scholarship Services at Fondren Library, Rice University
    Physical Address: 6100 Main Street, Houston, Texas 77005
    Mailing Address: MS-44, P.O.BOX 1892, Houston, Texas 77251-1892