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dc.contributor.advisor Cooper, Keith D.
dc.creatorBrogioli, Michael C.
dc.date.accessioned 2009-06-04T08:27:52Z
dc.date.available 2009-06-04T08:27:52Z
dc.date.issued 2003
dc.identifier.urihttps://hdl.handle.net/1911/17647
dc.description.abstract In order to curb microprocessor power consumption, we propose an L1 data cache which can be reconfigured dynamically at runtime according to the cache requirements of a given application. A two phase approach is used involving both compile time information, and the runtime monitoring of program performance. The compiler predicts L1 data cache requirements of loop nests in the input program, and instructs the hardware on how much L1 data cache to enable during a loop nest's execution. For regions of the program not analyzable at compile time, the hardware itself monitors program performance and reconfigures the L1 data cache so as to maintain cache performance while minimizing cache power consumption. In addition to this, we provide a study of data reuses inside loop nests of the SPEC CPU2000 and Mediabench benchmarks. The sensitivity of data reuses to L1 data cache associativity is analyzed to illustrated the potential power savings a reconfigurable L1 data cache can achieve.
dc.format.extent 72 p.
dc.format.mimetype application/pdf
dc.language.iso eng
dc.subjectElectronics
Electrical engineering
Computer science
dc.title Dynamically reconfigurable data caches in low-power computing
dc.type.genre Thesis
dc.type.material Text
thesis.degree.department Computer Science
thesis.degree.discipline Engineering
thesis.degree.grantor Rice University
thesis.degree.level Masters
thesis.degree.name Master of Science
dc.identifier.citation Brogioli, Michael C.. "Dynamically reconfigurable data caches in low-power computing." (2003) Master’s Thesis, Rice University. https://hdl.handle.net/1911/17647.


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