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dc.contributor.advisor Cavallaro, Joseph R.
dc.creatorChandrasekhar, Vikram
dc.date.accessioned 2009-06-04T08:43:23Z
dc.date.available 2009-06-04T08:43:23Z
dc.date.issued 2003
dc.identifier.urihttps://hdl.handle.net/1911/17582
dc.description.abstract Reduction of the power consumption in portable wireless receivers is an important consideration for next-generation cellular systems specified by standards such as the UMTS, IMT2000. This thesis explores the design-space for reducing the dynamic power dissipation in a RAKE receiver for the Direct Sequence Code Division Multiple Access (DS-CDMA) downlink. Starting with a reference implementation of the DS-CDMA RAKE receiver, we demonstrate design methodologies for achieving significant power reduction, while high-lighting the corresponding performance trade-offs. At the algorithm level, we investigate the impact of reduced precision and arithmetic complexity on the performance of the DS-CDMA RAKE receiver. We then present architectures for implementing the reference and reduced complexity DS-CDMA RAKE receivers, and analyze these architectures with respect to their dynamic power dissipation. Finally, we analyze clock-gating techniques for reducing the activity rate in both the architectures to achieve further power reduction.
dc.format.extent 70 p.
dc.format.mimetype application/pdf
dc.language.iso eng
dc.subjectElectronics
Electrical engineering
dc.title Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers
dc.type.genre Thesis
dc.type.material Text
thesis.degree.department Electrical and Computer Engineering
thesis.degree.discipline Engineering
thesis.degree.grantor Rice University
thesis.degree.level Masters
thesis.degree.name Master of Science
dc.identifier.citation Chandrasekhar, Vikram. "Reducing dynamic power consumption in next generation DS-CDMA mobile communication receivers." (2003) Master’s Thesis, Rice University. https://hdl.handle.net/1911/17582.


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