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dc.contributor.advisor Adve, Sarita V.
dc.creatorPai, Vijay Sadananda
dc.date.accessioned 2009-06-04T08:18:20Z
dc.date.available 2009-06-04T08:18:20Z
dc.date.issued 1997
dc.identifier.urihttp://hdl.handle.net/1911/17116
dc.description.abstract Current microprocessors exploit high levels of instruction-level parallelism (ILP). This thesis presents the first detailed analysis of the impact of such processors on shared-memory multiprocessors. We find that ILP techniques substantially reduce CPU time in multiprocessors, but are less effective in reducing memory stall time for our applications. Consequently, despite the latency-tolerating techniques incorporated in ILP processors, memory stall time becomes a larger component of execution time and parallel efficiencies are generally poorer in our ILP-based multiprocessor than in an otherwise equivalent previous-generation multiprocessor. We identify clustering independent read misses together in the processor instruction window as a key optimization to exploit the ILP features of current processors. We also use the above analysis to examine the validity of direct-execution simulators with previous-generation processor models to approximate ILP-based multiprocessors. We find that, with appropriate approximations, such simulators can reasonably characterize the behavior of applications with poor overlap of read misses. However, they can be highly inaccurate for applications with high overlap of read misses.
dc.format.extent 57 p.
dc.format.mimetype application/pdf
dc.language.iso eng
dc.subjectElectronics
Electrical engineering
Computer science
dc.title The impact of instruction-level parallelism on multiprocessor performance and simulation methodology
dc.type.genre Thesis
dc.type.material Text
thesis.degree.department Computer Science
thesis.degree.discipline Engineering
thesis.degree.grantor Rice University
thesis.degree.level Masters
thesis.degree.name Master of Science
dc.identifier.citation Pai, Vijay Sadananda. (1997) "The impact of instruction-level parallelism on multiprocessor performance and simulation methodology." Masters Thesis, Rice University. http://hdl.handle.net/1911/17116.


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