REDUCED BANDWIDTH DELTA NETWORKS
HARPER, DAVID TENNYSON, III
Doctor of Philosophy
As multiprocessor architectures become more prevalent, understanding the performance of interconnection networks becomes more critical. Because the cost of these networks is high, it is desirable to use the least sophisticated network which will not degrade system performance. By considering a more general model of delta networks it is shown that the full bandwidth of these networks cannot be utilized in many situations and that the amount of network bandwidth that can be utilized varies from application to application. Because the bandwidth required to support a given application does vary, it is desirable to evaluate the performance of a family of networks whose members have lower bandwidths than do delta networks. From this family of hybrid networks the choice of interconnection network can be made such that system cost is minimized while system performance remains unchanged. Since VLSI is the predominant implementation technique in current computer systems the constraints imposed on network design by VLSI must also be considered. In particular, the I/O bottleneck caused by pin limitations may force the network to be partitioned over multiple VLSI packages. How the network is partitioned greatly impacts the level of system performance. Additionally, implementation of networks in VLSI presents an alternative method of reducing system cost. This is accomplished through reduction in network data path width. Under some conditions this technique is a better method of reducing system cost than is the use of hybrid networks.
Electronics; Electrical engineering