MODELING OF LATERAL P-N JUNCTION DIODES IN POLYSILICON FILMS (GRAIN BOUNDARY, LIFETIME)
Doctor of Philosophy
Polysilicon is believed to be a key element for continued evolution of silicon integrated circuits. Recent advances in radiation processing and passivation techniques have enhanced the possibility of realizing acceptable active devices in polysilicon thin films. Of late, MOS devices fabricated in polysilicon do hold up a distinct possibility of achieving 3-D integration for higher packing density. P-n junction diode constitutes an essential element of any device. It is therefore imperative to have a quantitative model of p-n junction diodes in polysilicon. In this thesis, a model for the polysilicon p-n junction diodes is developed. The present model is based on incorporating the effective minority carrier lifetime operative in crystalline grain and amorphous conducting boundary. The bulk resistance effect especially at lower doping levels is accounted for. In addition, in the present model, the grain boundaries parallel to the current flow in the junction depletion depth are shown to serve as ohmic conduction channels. This additional amorphous channel can account for the unusually high current level observed at small applied voltages. The role of grain boundary in affecting minority carrier diffusion processes is illustrated by considering the presence of one grain boundary in the analysis of continuity equation operative in minority carrier diffusion region.