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dc.contributor.advisor Cavallaro, Joseph R.
dc.creatorSengupta, Chaitali
dc.date.accessioned 2009-06-04T00:24:27Z
dc.date.available 2009-06-04T00:24:27Z
dc.date.issued 1995
dc.identifier.urihttps://hdl.handle.net/1911/13995
dc.description.abstract This thesis presents an Integrated CAD Framework which links VLSI layout editors to lithographic simulators and provides information on the simulated resolution of a feature to the circuit designer. This will help designers to design more compact circuits, as they will be able to see the effect on manufactured silicon. The Framework identifies areas in a layout (in Magic or CIF format) that are more prone to problems arising out of the photolithographic process. It then creates the corresponding inputs for closer analysis with a process simulator (Depict) and analyzes the simulator outputs to decide whether the printed layout will match the designed mask for a particular set of process parameters. The designer can modify the original layout based upon this analysis. The Framework has been used to evaluate layouts for various process techniques. These evaluations illustrate the use of the Framework in determining the limits of any lithographic process.
dc.format.extent 91 p.
dc.format.mimetype application/pdf
dc.language.iso eng
dc.subjectElectronics
Electrical engineering
Industrial engineering
dc.title An integrated CAD framework linking VLSI layout editors and process simulators
dc.type.genre Thesis
dc.type.material Text
thesis.degree.department Electrical and Computer Engineering
thesis.degree.discipline Engineering
thesis.degree.grantor Rice University
thesis.degree.level Masters
thesis.degree.name Master of Science
dc.identifier.citation Sengupta, Chaitali. "An integrated CAD framework linking VLSI layout editors and process simulators." (1995) Master’s Thesis, Rice University. https://hdl.handle.net/1911/13995.


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