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dc.contributor.advisor Cavallaro, Joseph R.
dc.creatorHemkumar, Nariankadu Datatreya
dc.date.accessioned 2009-06-04T00:35:17Z
dc.date.available 2009-06-04T00:35:17Z
dc.date.issued 1991
dc.identifier.urihttps://hdl.handle.net/1911/13526
dc.description.abstract This thesis presents a systolic algorithm for the SVD of arbitrary complex matrices, based on the cyclic Jacobi method with "parallel ordering". As a basic step in the algorithm, a two-step, two-sided unitary transformation scheme is employed to diagonalize a complex 2 $\times$ 2 matrix. The transformations are tailored to the use of CORDIC (COordinate Rotation DIgital Computer) algorithms for high speed arithmetic. The complex SVD array is modeled on the Brent-Luk-VanLoan array for real SVD. An array with O($n\sp2$) processors is required to compute the SVD of a $n \times n$ matrix in O(n log n) time. An architecture for the complex 2 $\times$ 2 processor with an area complexity twice that of a real 2 $\times$ 2 processor, is shown to have the best area/time tradeoff for VLSI implementation. Despite the involved nature of computations on complex data, the computation time for the complex SVD array is less than three times that for a real SVD array with a similar CORDIC based implementation.
dc.format.extent 122 p.
dc.format.mimetype application/pdf
dc.language.iso eng
dc.subjectElectronics
Electrical engineering
Computer science
dc.title A systolic VLSI architecture for complex SVD
dc.type.genre Thesis
dc.type.material Text
thesis.degree.department Computer Science
thesis.degree.discipline Engineering
thesis.degree.grantor Rice University
thesis.degree.level Masters
thesis.degree.name Master of Science
dc.identifier.citation Hemkumar, Nariankadu Datatreya. "A systolic VLSI architecture for complex SVD." (1991) Master’s Thesis, Rice University. https://hdl.handle.net/1911/13526.


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