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dc.contributor.advisor Jump, J. Robert
dc.contributor.advisor Sinclair, James B.
dc.creatorFoundoulis, William James
dc.date.accessioned 2009-06-04T00:39:38Z
dc.date.available 2009-06-04T00:39:38Z
dc.date.issued 1989
dc.identifier.urihttp://hdl.handle.net/1911/13357
dc.description.abstract In this study we discuss the development and validation of an efficient and accurate execution-driven simulation of the Texas Instruments Odyssey System, a parallel configuration of digital signal processors. We also evaluate the performance of a high-level parallel programming interface, Odyssey Concurrent C, designed to effectively utilize the parallelism available in the Odyssey architecture. Parallel versions of three dissimilar algorithms--merge sort, 2-dimensional convolution, and successive over-relaxation--have been run on both the Odyssey and the simulator. Quantitative differences between performance results obtained on the Odyssey and those predicted by simulation are enumerated, and shown to validate the accuracy of the execution-driven approach. The simulation is also shown to be efficient relative to the degree of accuracy obtainable. Finally, the Odyssey Concurrent C utilities are shown to provide a flexible and effective mechanism for managing parallelism in the Odyssey environment.
dc.format.extent 72 p.
dc.format.mimetype application/pdf
dc.language.iso eng
dc.subjectElectronics
Electrical engineering
Computer science
dc.title Efficient simulation and utilization of a parallel digital signal processing architecture
dc.type.genre Thesis
dc.type.material Text
thesis.degree.department Computer Science
thesis.degree.discipline Engineering
thesis.degree.grantor Rice University
thesis.degree.level Masters
thesis.degree.name Master of Science
dc.identifier.citation Foundoulis, William James. "Efficient simulation and utilization of a parallel digital signal processing architecture." (1989) Master’s Thesis, Rice University. http://hdl.handle.net/1911/13357.


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