Modeling and variability aware design techniques for mixed signal systems
Doctor of Philosophy
The tremendous advancement in the field of integrated circuit manufacturing achieved in the past decade can largely be attributed to the successful continuous scaling of CMOS technology combined with the increase in the operating frequencies. However, the continuous feature scaling has significantly increased the impact of process variation on the performance of deep submicron integrated circuits. Process variation has become a major concern for designers since the fabricated circuit performance can vary dramatically from the predicted designed performance leading to a significant yield loss. Variability-aware design techniques have emerged as a potential solution that considers the process variation effects during the design stage. In this dissertation, we develop variability-aware design techniques for mixed-signal systems that can mitigate the impact of process variation and generate robust circuits and systems. Since Network-on-Chip (NoC) is the potential alternative for the traditional common-bus architectures specially for multi-core digital systems, we analyze the delay variation in NoC interconnects due to process variation. We develop Elmore delay based model for the delay variability in the buffered links due to the variation in the effective channel length because of lithographic errors and the variation in the interconnect parasitic resistance because of dishing. Furthermore, we develop closed form expression for probability of link failure due to delay variation in order to optimize the clock slack for minimum delay. Our simulation results demonstrate the effectiveness of this design technique. In addition, we present a new dynamic routing algorithm that has the ability to solve the physical layer problems such as static faults and electromigration effects by leveraging higher network layers. Our algorithm utilizes the communication signals between the neighbour routers to avoid the faulty links and to balance the AC currents on each link in order to alleviate the electromigration aging process. Our simulation results depict the improvement in the average latency and energy consumption using our fault-aware dynamic routing algorithm, while the results show the boost in the expected lifetime of the chip using our electromigration-aware dynamic routing algorithm. Due to the crucial importance of Low Noise Amplifier (LNA) as the performance bottleneck for RF receivers for either on-chip interconnects or off-chip wireless communication, in this dissertation, we develop different variability-aware design techniques that can mitigate the impact of process variation on the LNA performance dramatically. We develop an analytical modeling technique for both narrow band and wideband LNAs combined with a hierarchical design optimization platform to generate the required design specifications under system-on-chip integration constraints. In order to demonstrate the universality of our variability-aware design techniques for other analog/RF circuits, we leverage our presented design platform to optimize the design for LNA/Mixer pair. Our simulation results illustrate the success of our design techniques in achieving the required robust performance. Finally, we present a prototype hardware for compressive sensing based analog-to-information converters (AICs) that enables efficient communication for either on-chip or off-chip applications. We also present a behavioral modeling technique to evaluate the performance of the compressive sensing based applications.