Logic design for reliability

Abstract

Reliability of logic circuits is emerging as an important concern that may limit the benefits of continued scaling of process technology and the emergence of future technology alternatives. Scaling of CMOS devices below 100nm has revealed their vulnerability to process variations, thermodynamic variations, transient errors due to radiation, electromagnetic interference and extreme scaling effects. Variations cause the output of gates to deviate from the correct value potentially leading to logic errors. The search for new devices to replace CMOS in the future has led to advances in the synthesis and self-assembly of nanoelectronic devices like carbon nanotube transistors that indicate the ability to manufacture dense nanoelectronic fabrics. However, the tremendous device densities afforded by nanoelectronic technologies is expected to be accompanied by substantial increases in defect densities, transient error rates, and performance variability. Thus, high failure rates are inherent to computing devices of the future and have led to an increased interest in investigating the potential of logic design techniques to improve circuit reliability. This thesis contributes to two major aspects of logic design for circuit reliability: (1) Computing the reliability of logic circuits built with unreliable devices. (2) Detection of errors in logic circuits based on approximate logic functions.