Browsing by Author "Pai, Vijay S."
Now showing items 1-20 of 23
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Challenges in Computer Architecture Evaluation
(2003-08-20)A report to the US National Science Foundation argues that simulation and benchmarking technology will require a leap in capability within the next few years to maintain ongoing innovation in computer systems. -
Code Transformations to Improve Memory Parallelism
(2000-05-20)Current microprocessors incorporate techniques to exploit instruction-level parallelism (ILP). However, previous work has shown that these ILP techniques are less effective in removing memory stall time than CPU time, ... -
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A Customized MVA Model for ILP Multiprocessors
(1998-04-20)This paper provides the customized MVA equations for an analytical model for evaluating architectural alternatives for shared-memory multiprocessors with processors that aggressively exploit instruction-level parallelism ... -
Exploiting Instruction-Level Parallelism for Memory System Performance
(2000-08-20)Current microprocessors improve performance by exploiting instruction-level parallelism (ILP). ILP hardware techniques such as multiple instruction issue, out-of-order (dynamic) issue, and non-blocking reads can accelerate ... -
Exploiting Task-Level Concurrency in a Programmable Network Interface
(2003-06-20)Programmable network interfaces provide the potential to extend the functionality of network services but lead to instruction processing overheads when compared to application-specific network interfaces. This paper aims ... -
A Flexible and Efficient Application Programming Interface (API) for a Customizable Proxy Cache
(2003-03-20)This paper describes the design, implementation, and performance of a simple yet powerful Application Programming Interface (API) for providing extended services in a proxy cache. This API facilitates the development of ... -
The Impact of Exploiting Instruction-Level Parallelism on Shared-Memory Multiprocessors
(1999-02-20)Current microprocessors incorporate techniques to aggressively exploit instruction-level parallelism (ILP). This paper evaluates the impact of such processors on the performance of shared-memory multiprocessors, both without ... -
The Impact of Instruction-Level Parallelism on Multiprocessor Performance and Simulation Methodology
(1997-04-20)Current microprocessors exploit high levels of instruction-level parallelism (ILP). This theis presents the first detailed analysis of the impact of such processors on shared-memory multiprocessors. We find that ILP ... -
Increasing Web Server Throughput with Network Interface Data Caching
(2002-10-20)This paper introduces network interface data caching, a new technique to reduce local interconnect traffic on networking servers by caching frequently-requested content on a programmable network interface. The operating ... -
Isolating the Performance Impacts of Network Interface Cards through Microbenchmarks
(2004-06-01)This paper studies the impact of network interface cards (NICs) on network server performance, testing six different Gigabit Ethernet NICs. Even with all other hardware and software configurations unchanged, a network ... -
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RSIM Reference Manual: Version 1.0
(1997-08-20)Simulation has emerged as an important method for evaluating new ideas in both uniprocessor and multiprocessor architecture. Compared to building real hardware, simulation provides at least two advantages. First it ...
