Now showing items 1-25 of 25

  • Architectures for Cognitive Radio Testbeds and Demonstrators – An Overview 

    Gustafsson, Oscar; Amiri, Kiarash; Andersson, Dennis; Blad, Anton; Bonner, Christian; Cavallaro, Joseph R.; Declerck, Jeroen; Dejonghe, Antoine; Eliardsson, Patrik; Glasse, Miguel; Hayar, Aawatif; Hollevoet, Lieven; Hunter, Chris; Joshi, Madhura; Kaltenberger, Florian; Knopp, Raymond; Le, Khanh; Miljanic, Zoran; Murphy, Patrick; Naessens, Frederik; Nikaein, Navid; Nussbaum, Dominique; Pacalet, Renaud; Raghavan, Praveen; Sabharwal, Ashutosh; Sarode, Onkar; Spasojevic, Predrag; Sun, Yang; Tullberg, Hugo M.; Vander Aa, Tom; Van der Perre, Liesbet; Wetterwald, Michelle; Wu, Michael (IEEE, 2010-06-01)
    Wireless communication standards are developed at an ever-increasing rate of pace, and significant amounts of effort is put into research for new communication methods and concepts. On the physical layer, such topics include ...
  • Complexity Analysis of MMSE Detector Architectures for MIMO OFDM Systems 

    Myllylä, Markus; Hintikka, Juha-Matti; Cavallaro, Joseph R.; Juntti, Markku; Limingoja, Matti; Byman, Aaron (IEEE, 2005-11-01)
    In this paper, a field programmable gate array (FPGA) implementation of a linear minimum mean square error (LMMSE) detector is considered for MIMO-OFDM systems. Two square root free algorithms based on QR decomposition ...
  • Design and Analysis of Heterogeneous DSP/FPGA Based Architectures for 3GPP Wireless Systems 

    Brogioli, Michael C.; Gadhiok, Manik; Cavallaro, Joseph R. (IEEE, 2006-04-01)
    This paper shows how iterative hardware/software partitioning in heterogeneous DSP/FPGA based embedded systems can be utilized to achieve real-time deadlines of modern 3GPP wireless equalization workloads. By utilizing a ...
  • Design and Architecture of Spatial Multiplexing MIMO Decoders for FPGAs 

    Dick, Chris; Amiri, Kiarash; Cavallaro, Joseph R.; Rao, Raghu (IEEE, 2008-10-01)
    Spatial multiplexing multiple-input-multiple-output (MIMO) communication systems have recently drawn significant attention as a means to achieve tremendous gains in wireless system capacity and link reliability. The optimal ...
  • Design of the Transit Access Point Hardware Platform 

    Murphy, Patrick; Frantz, Patrick; Aazhang, Behnaam (2005-09-01)
    Our objective is to design, analyze, prototype and experimentally study the theoretical underpinnings for a wireless internet that simultaneously achieves deployability, scalability, high performance and a cost-effective ...
  • Design, Implementation and Characterization of a Cooperative Communications System 

    Murphy, Patrick O. (2011)
    Cooperative communications is a class of techniques which seek to improve reliability and throughput in wireless systems by pooling the resources of distributed nodes. While cooperation can occur at different network layers ...
  • An FPGA Based Rapid Prototyping Platform for MIMO Systems 

    Murphy, Patrick; Lou, Feifei; Sabharwal, Ashutosh; Frantz, Patrick (2003-11-20)
    There exists a seemingly limitless demand for wireless communications systems capable of higher datarates with lower power consumption. While the demand for improvement in these systems seems limitless, the spectrum ...
  • An FPGA Implementation Of Alamouti's Transmit Diversity Technique 

    Murphy, Patrick; Frantz, Patrick; Dick, Chris (2003-10-01)
    This paper presents the FPGA implementation of a multiple antenna wireless communications system based on Alamouti's transmit diversity scheme. Alamouti's transmit diversty scheme is a space-time block code with support ...
  • FPGA Implementation of Matrix Inversion Using QRD-RLS Algorithm 

    Karkooti, Marjan; Cavallaro, Joseph R.; Dick, Chris (2005-11-01)
    This paper presents a novel architecture for matrix inversion by generalizing the QR decomposition-based recursive least square (RLS) algorithm. The use of Squared Givens rotations and a folded systolic array makes this ...
  • An FPGA-based Daughtercard for TIs C6000 family of DSKs 

    Gadhiok, Manik; Hardy, Ricky; Murphy, Patrick; Frantz, Patrick; Choi, Hyeokho; Cavallaro, Joseph R. (2005-06-01)
    In this paper we present an FPGA-based daughtercard designed for TIs C6000 family of DSP Starter Kits (DSKs). The hardware, initially designed for a course project, provides a platform for studying heterogeneous systems ...
  • A FPGA­Based Experimental PHY for 802.11b WLAN 

    Lou, Feifei; Murphy, Patrick; Frantz, Patrick (2003-10-20)
    The swift proliferation of wireless data communication systems, and the ever-increasing demand for faster data rates requires that engineers be able to quickly design, implement and test new wireless algorithms for data ...
  • A General Hardware/Software Co-design Methodology for Embedded Signal Processing and Multimedia Workloads 

    Brogioli, Michael; Radosavljevic, Predrag; Cavallaro, Joseph R. (IEEE, 2006-11-01)
    This paper presents a hardware/software co-design methodology for partitioning real-time embedded multimedia applications between software programmable DSPs and hardware based FPGA coprocessors. By following a strict set ...
  • HIGH THROUGHPUT, PARALLEL, SCALABLE LDPC ENCODER/DECODER ARCHITECTURE FOR OFDM SYSTEMS 

    Sun, Yang; Karkooti, Marjan; Cavallaro, Joseph R. (IEEE, 2006-10-01)
    This paper presents a high throughput, parallel, scalable and irregular LDPC coding and decoding system hardware implementation that supports twelve combinations of block lengths 648, 1296, 1944 bits and code rates 1/2, ...
  • Implementation and Complexity Analysis of List Sphere Detector for MIMO-OFDM systems 

    Myllylä, Markus; Juntti, Markku; Cavallaro, Joseph R. (IEEE, 2008-10-01)
    A list sphere detector (LSD) is an enhancement of a sphere detector (SD) that can be used to approximate the soft output maximum a posteriori probability (MAP) detector used in the detection of the multiple-input ...
  • Low Complexity Opportunistic Decoder for Network Coding 

    Yin, Bei; Wu, Michael; Wang, Guohui; Cavallaro, Joseph R. (IEEE, 2012-12-01)
    In this paper, we propose a novel opportunistic decoding scheme for network coding decoder which significantly reduces the decoder complexity and increases the throughput. Network coding was proposed to improve the ...
  • Low complexity scalable MIMO sphere detection through antenna detection reordering 

    Wu, Michael; Dick, Chris; Sun, Yang; Cavallaro, Joseph R. (Springer, 2012-07-01)
    This paper describes a novel low complexity scalable multiple-input multiple-output (MIMO) detector that does not require preprocessing and the optimal squared l2-norm computations to achieve good bit error (BER) performance. ...
  • LTE uplink MIMO receiver with low complexity interference cancellation 

    Yin, Bei; Cavallaro, Joseph R. (Sprnger, 2012-11-01)
    In LTE/LTE-A uplink receiver, frequency domain equalizers (FDE) are adopted to achieve good performance. However, in multi-tap channels, the residual inter-symbol and inter-antenna interference still exist after FDE ...
  • Parallel VLSI Architectures for Multi-Gbps MIMO Communication Systems 

    Sun, Yang (2011)
    In wireless communications, the use of multiple antennas at both the transmitter and the receiver is a key technology to enable high data rate transmission without additional bandwidth or transmit power. Multiple-input ...
  • Performance - Complexity Comparison of Receivers for a LTE MIMO–OFDM System 

    Ketonen, Johanna; Juntti, Markku; Cavallaro, Joseph R. (IEEE, 2010-06-01)
    Implementation of receivers for spatial multiplexing multiple-input multiple-output (MIMO) orthogonal-frequency-division-multiplexing (OFDM) systems is considered. The linear minimum mean-square error (LMMSE) and the K-best ...
  • Performance Evaluation of Two LMMSE Detectors in a MIMO-OFDM Hardware Testbed 

    Myllylä, Markus; Juntti, Markku; Limingoja, Matti; Byman, Aaron; Cavallaro, Joseph R. (IEEE, 2006-11-01)
    The performance of two field programmable gate array (FPGA) implementations of a linear minimum mean square error (LMMSE) based detector is evaluated in real-time radio channels. Two square root free algorithms based on ...
  • Prototyping Platforms for Multiple Antenna Wireless Communications 

    Murphy, Patrick (2005-04-01)
    As the demand for higher performance wireless communications continues to grow, novel algorithms have been developed which provide increased performance and efficiency. One such class of algorithms involves the use of ...
  • Scalable FPGA Architectures for LMMSE-based SIMO Chip Equalizer in HSDPA Downlink 

    Guo, Yuanbin; McCain, Dennis; Zhang, Jianzhong (Charlie); Cavallaro, Joseph R. (IEEE, 2003-11-01)
    In this paper, scalable FPGA architectures for the LMMSE-based chip-level equalizer in HSDPA downlink re-ceivers are studied. An FFT-based algorithm is applied to avoid the direct matrix inverse by utilizing the block-Toeplitz ...
  • VITURBO: A Reconfigurable Architecture for Ubiquitous Wireless Networks 

    Vaya, Mani (2002-08-01)
    A run-time reconfigurable architecture for ubiquitous wireless networks has been designed and implemented. Reconfigurable architectures have the ability to change themselves dynamically thus presenting a viable proposition ...
  • VLSI Architectures for Multitier Wireless Systems 

    Cavallaro, Joseph R. (1999-11-20)
    Next-generation computing systems will be highly integrated using wireless networking. The Rice Everywhere NEtwork (RENÃ ) project is exploring the integration of WCDMA cellular systems, high speed wireless LANs, and home ...
  • W-CDMA real-time algorithm implementation and evaluation 

    Jones, Bryan Allen (2000-05-20)
    This paper describes a platform to enable and explore the design and implementation of next-generation CDMA wireless base stations. A DSP and FPGA-based multiprocessor board is integrated into a Simulink-based wireless ...