Now showing items 1-2 of 2

    • Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations 

      Cavallaro, Joseph R.; Sengupta, Chaitali; Tittel, Frank K.; Wilson, William L. Jr. (1996-01-01)
      This paper describes a CAD tool (An Integrated CAD Framework) which links VLSI layout editors to lithographic simulators and provides information on the simulated resolution of a feature to the circuit designer. The designer ...
    • An Integrated CAD Framework Linking VLSI Layout Editors and Process Simulators 

      Sengupta, Chaitali; Erdelyi, Miklos; Bor, Zsolt; Cavallaro, Joseph R.; Smayling, Michael C.; Szabo, Gabor; Tittel, Frank K.; Wilson, William L. (1996-03-01)
      As feature sizes in VLSI circuits extend into the far sub-micron range, new process techniques, such as using phase shifting masks for photolithography, will be needed. Under these conditions, the only means for the circuit ...