| Files | Size | Format | View |
|---|---|---|---|
| CHAPTER 8-Introduction.pdf | 10.37Kb | application/pdf |
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| dc.contributor.author | Sun, Yang Amiri, Kiarash Wang, Guohui Yin, Bei Cavallaro, Joseph R. Ly, Tai |
|---|---|
| dc.date.accessioned | 2012-07-26T15:33:44Z |
| dc.date.available | 2012-07-26T15:33:44Z |
| dc.date.issued | 2012-07-12 |
| dc.identifier.other | http://store.elsevier.com/product.jsp?isbn=9780123865359&_requestid=111075 |
| dc.identifier.uri | http://hdl.handle.net/1911/64508 |
| dc.description.abstract | High-level synthesis design methodology - High level synthesis (HLS) [1], also known as behavioral synthesis and algorithmic synthesis, is a design process in which a high level, functional description of a design is automatically compiled into a RTL implementation that meets certain user specified design constraints. The HLS design description is ‘high level’ compared to RTL in two aspects: design abstraction, and specification language. |
| dc.publisher | Elsevier, Waltham, MA |
| dc.title | High-Level Design Tools for Complex DSP Applications |
| dc.type | Book chapter |
| dc.contributor.center | Center for Multimedia Communication |
| dc.citation.volumeNumber | Chapter 8 |
| dc.citation.pageNumber | 133-155 |
| dc.identifier.citation | Y. Sun, K. Amiri, G. Wang, B. Yin, J. R. Cavallaro and T. Ly, "High-Level Design Tools for Complex DSP Applications," vol. Chapter 8, pp. 133-155, 2012. |