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Title:
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High-Level Design Tools for Complex DSP Applications |
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Author:
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Sun, Yang; Amiri, Kiarash; Wang, Guohui; Yin, Bei; Cavallaro, Joseph R.; Ly, Tai
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Type:
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Book chapter |
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Publisher:
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Elsevier, Waltham, MA |
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Citation:
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Y. Sun, K. Amiri, G. Wang, B. Yin, J. R. Cavallaro and T. Ly, "High-Level Design Tools for Complex DSP Applications," vol. Chapter 8, pp. 133-155, 2012. |
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Abstract:
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High-level synthesis design methodology - High level synthesis (HLS) [1], also known as behavioral synthesis and algorithmic synthesis, is a design
process in which a high level, functional description of a design is automatically compiled into a RTL implementation that meets certain user specified design constraints. The HLS design description is ‘high
level’ compared to RTL in two aspects: design abstraction, and specification language. |
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Date Published:
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2012-07-12 |
