deposit_your_work

High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm

Files in this item

Files Size Format View
2012_TRANS_VLSI_Sun.pdf 1.295Mb application/pdf Thumbnail

Show simple item record

Item Metadata

dc.contributor.author Sun, Yang
Cavallaro, Joseph R.
dc.date.accessioned 2012-06-22T20:48:29Z
dc.date.available 2012-06-22T20:48:29Z
dc.date.issued 2012-07-01
dc.identifier.other http://scholar.google.com/scholar?q=High-Throughput+Soft-Output+MIMO+Detector+Based+on+Path-Preserving+Trellis-Search+Algorithm&btnG=&hl=en&as_sdt=0%2C44
dc.identifier.uri http://hdl.handle.net/1911/64295
dc.description.abstract In this paper, we propose a novel path-preserving trellis-search (PPTS) algorithm and its high-speed VLSI architecture for soft-output multiple-input-multiple-output (MIMO) detection. We represent the search space of the MIMO signal with an unconstrained trellis, where each node in stage of the trellis maps to a possible complex-valued symbol transmitted by antenna. Based on the trellis model, we convert the soft-output MIMO detection problem into a multiple shortest paths problem subject to the constraint that every trellis node must be covered in this set of paths. The PPTS detector is guaranteed to have soft information for every possible symbol transmitted on every antenna so that the log-likelihood ratio (LLR) for each transmitted data bit can be more accurately formed. Simulation results show that the PPTS algorithm can achieve near-optimal error performance with a low search complexity. The PPTS algorithm is a hardware-friendly data-parallel algorithm because the search operations are evenly distributed among multiple trellis nodes for parallel processing. As a case study, we have designed and synthesized a fully-parallel systolic-array detector and two folded detectors for a 4x4 16-QAM system using a 1.08 V TSMC 65-nm CMOS technology.With a 1.18 mm2 core area, the folded detector can achieve a throughput of 2.1 Gbps.With a 3.19 mm2 core area, the fully-parallel systolic-array detector can achieve a throughput of 6.4 Gbps.
dc.publisher IEEE
dc.subject Application-specific integrated circuit (ASIC)
Multiple-input-multiple-output (MIMO) detection
Shortest path algorithm
Soft output MIMO detector
VLSI architecture
dc.title High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm
dc.type Journal Paper
dc.citation.journalTitle IEEE Transactions on VLSI Systems
dc.contributor.center Center for Multimedia Communication
dc.citation.volumeNumber 20
dc.citation.pageNumber 1235-1247
dc.citation.issueNumber 7
dc.identifier.citation Y. Sun and J. R. Cavallaro, "High-Throughput Soft-Output MIMO Detector Based on Path-Preserving Trellis-Search Algorithm," IEEE Transactions on VLSI Systems, vol. 20, no. 7, pp. 1235-1247, 2012.

This item appears in the following Collection(s)

  • ECE Publications [1082 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • CMC Publications [275 items]
    Publications by Rice Faculty and graduate students in multimedia communications