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Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations

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Title: Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations
Author: Cavallaro, Joseph R.; Sengupta, Chaitali; Tittel, Frank K.; Wilson, William L. Jr.
Type: Conference Paper
Publisher: SME Press
Citation: J. R. Cavallaro, C. Sengupta, F. K. Tittel and W. L. J. Wilson,"Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations," in NSF Design and Manufacturing Grantees Conference, 1996, pp. 345-346.
Abstract: This paper describes a CAD tool (An Integrated CAD Framework) which links VLSI layout editors to lithographic simulators and provides information on the simulated resolution of a feature to the circuit designer. The designer can modify the original layout based upon this analysis to create compact circuits with better yield capabilities. The objective of this project is to improve the manufacturability of high density VLSI integrated circuits.
Date Published: 1996-01-01

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  • ECE Publications [1032 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • CMC Publications [275 items]
    Publications by Rice Faculty and graduate students in multimedia communications