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VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes

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Title: VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes
Author: Sun, Yang; Karkooti, Marjan; Cavallaro, Joseph R.
Type: Conference Paper
Publisher: IEEE
Citation: Y. Sun, M. Karkooti and J. R. Cavallaro,"VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes," in IEEE International Symposium on Circuits and Systems (ISCAS), 2007, pp. 2104-2107.
Abstract: A low-density parity-check (LDPC) decoder architecture that supports variable block sizes and multiple code rates is presented. The proposed architecture is based on the structured quasi-cyclic (QC-LDPC) codes whose performance compares favorably with that of randomly constructed LDPC codes for short to moderate block sizes. The main contribution of this work is to address the variable block-size and multirate decoder hardware complexity that stems from the irregular LDPC codes. The overall decoder, which was synthesized, placed and routed on TSMC 0.13-micron CMOS technology with a core area of 4.5 square millimeters, supports variable code lengths from 360 to 4200 bits and multiple code rates between 1/4 and 9/10. The average throughput can achieve 1 Gbps at 2.2 dB SNR.
Date Published: 2007-05-01

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