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Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4GWireless Standards

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Title: Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4GWireless Standards
Author: Sun, Yang; Zhu, Yuming; Goel, Manish; Cavallaro, Joseph R.
Type: Conference paper
Publisher: IEEE
Citation: Y. Sun, Y. Zhu, M. Goel and J. R. Cavallaro, "Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4GWireless Standards," pp. 209-214, 2008.
Abstract: In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posteriori) decoder is designed for both binary and duo-binary turbo codes with small resource overhead (less than 10%) compared to the single-mode architecture. To achieve high data rates in 4G, we present a parallel turbo decoder architecture with scalable parallelism tailored to the given throughput requirements. High-level parallelism is achieved by employing contention-free interleavers. Multi-banked memory structure and routing network among memories and MAP decoders are designed to operate at full speed with parallel interleavers. We designed a very low-complexity recursive on-line address generator supporting multiple interleaving patterns, which avoids the interleaver address memory. Design trade-offs in terms of area and power efficiency are explored to find the optimal architectures. A 711 Mbps data rate is feasible with 32 Radix-4 MAP decoders running at 200 MHz clock rate.
Date Published: 2008-07-01

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    Publications by Rice Faculty and graduate students in multimedia communications