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Title:
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Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4GWireless Standards |
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Author:
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Sun, Yang; Zhu, Yuming; Goel, Manish; Cavallaro, Joseph R.
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Type:
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Conference Paper |
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Publisher:
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IEEE |
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Citation:
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Y. Sun, Y. Zhu, M. Goel and J. R. Cavallaro,"Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4GWireless Standards," in IEEE International Conference on Application-Specific System, Architectures and Processors (ASAP), 2008, pp. 209-214. |
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Abstract:
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In this paper, we propose a novel multi-code turbo decoder architecture for 4G wireless systems. To support various 4G standards, a configurable multi-mode MAP (maximum a posteriori) decoder is designed for both binary and duo-binary turbo codes with small resource overhead (less than 10%) compared to the single-mode architecture. To achieve high data rates in 4G, we present a parallel turbo decoder architecture with scalable parallelism tailored to the given throughput requirements. High-level parallelism is achieved by employing contention-free interleavers. Multi-banked memory structure and routing network among memories and MAP decoders are designed to operate at full speed with parallel interleavers. We designed a very low-complexity recursive on-line address generator supporting multiple interleaving patterns, which avoids the interleaver address memory. Design trade-offs in terms of area and power efficiency are explored to find the optimal architectures. A 711 Mbps data rate is feasible with 32 Radix-4 MAP decoders running at 200 MHz clock rate. |
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Date Published:
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2008-07-01 |
