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UNIFIED DECODER ARCHITECTURE FOR LDPC/TURBO CODES

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Title: UNIFIED DECODER ARCHITECTURE FOR LDPC/TURBO CODES
Author: Sun, Yang; Cavallaro, Joseph R.
Type: Conference Paper
Publisher: IEEE
Citation: Y. Sun and J. R. Cavallaro,"UNIFIED DECODER ARCHITECTURE FOR LDPC/TURBO CODES," in IEEE Workshop on Signal Processing Systems (SIPS), 2008, pp. 13-18.
Abstract: Low-density parity-check (LDPC) codes on par with convolutional turbo codes (CTC) are two of the most powerful error correction codes known to perform very close to the Shannon limit. However, their different code structures usually lead to different hardware implementations. In this paper, we propose a unified decoder architecture that is capable of decoding both LDPC and turbo codes with a limited hardware overhead. We employ maximum a posteriori (MAP) algorithm as a bridge between LDPC and turbo codes. We represent LDPC codes as parallel concatenated single parity check (PCSPC) codes and propose a group sub-trellis (GST) decoding algorithm for the efficient decoding of PCSPC codes. This algorithm achieves about 2X improvement in the convergence speed and is more numerically robust than the classical ”tanh” algorithm. What is more interesting is that we can generalize a unified trellis decoding algorithm for LDPC and turbo codes based on their trellis structures. We propose a reconfigurable computation kernel for log-MAP decoding of LDPC and turbo codes at a cost of ∼15% hardware overhead. Small lookup tables (LUTs) with 9 entries of 2-bit data are designed to implement the log-MAP algorithm. Fixed point (6:2) simulation results show that there is negligible or nearly no performance loss by using this LUT approximation compared to the ideal case. The proposed architecture results in scalable and flexible datapath units enabling parallel decoding of LDPC/turbo codes.
Date Published: 2008-10-01

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    Publications by Rice Faculty and graduate students in multimedia communications