deposit_your_work

Scalable and Low Power LDPC Decoder Design Using High Level Algorithmic Synthesis

Files in this item

Files Size Format View
2009_SOC_Sun.pdf 480.8Kb application/pdf Thumbnail

Show full item record

Item Metadata

Title: Scalable and Low Power LDPC Decoder Design Using High Level Algorithmic Synthesis
Author: Sun, Yang; Cavallaro, Joseph R.; Ly, Tai
Type: Conference Paper
Publisher: IEEE
Citation: Y. Sun, J. R. Cavallaro and T. Ly,"Scalable and Low Power LDPC Decoder Design Using High Level Algorithmic Synthesis," in IEEE International System-on-Chip (SOC) Conference, 2009, pp. 267-270.
Abstract: This paper presents a scalable and low power low-density parity-check (LDPC) decoder design for the next generation wireless handset SoC. The methodology is based on high level synthesis: PICO (program-in chip-out) tool was used to produce efficient RTL directly from a sequential untimed C algorithm. We propose two parallel LDPC decoder architectures: (1) per-layer decoding architecture with scalable parallelism, and (2) multi-layer pipelined decoding architecture to achieve higher throughput. Based on the PICO technology, we have implemented a two-layer pipelined decoder on a TSMC 65nm 0.9V 8-metal layer CMOS technology with a core area of 1.2 mm2. The maximum achievable throughput is 415 Mbps when operating at 400 MHz clock frequency and the estimated peak power consumption is 180 mW.
Date Published: 2009-09-01

This item appears in the following Collection(s)

  • ECE Publications [1032 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • CMC Publications [275 items]
    Publications by Rice Faculty and graduate students in multimedia communications