deposit_your_work

An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture

Files in this item

Files Size Format View
2006_EURASIP_Equalizer_Guo_057134.pdf 799.8Kb application/pdf Thumbnail

Show full item record

Item Metadata

Title: An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture
Author: Guo, Yuanbin; Zhang, Jianzhong; McCain, Dennis; Cavallaro, Joseph R.
Type: Journal Paper
Publisher: Hindawi Publishing Corporation
Citation: Y. Guo, J. Zhang, D. McCain and J. R. Cavallaro, "An Efficient Circulant MIMO Equalizer for CDMA Downlink: Algorithm and VLSI Architecture," EURASIP Journal on Applied Signal Processing, vol. 2006, no. Article ID 57134, pp. 1-18, 2006.
Abstract: We present an efficient circulant approximation-based MIMO equalizer architecture for the CDMA downlink. This reduces the direct matrix inverse (DMI) of size (NF×NF) with O((NF)3) complexity to some FFT operations with O(NF log2(F)) complexity and the inverse of some (N×N) submatrices.We then propose parallel and pipelined VLSI architectures with Hermitian optimization and reduced-state FFT for further complexity optimization. Generic VLSI architectures are derived for the (4×4) high-order receiver from partitioned (2 × 2) submatrices. This leads to more parallel VLSI design with 3× further complexity reduction. Comparative study with both the conjugate-gradient and DMI algorithms shows very promising performance/complexity tradeoff. VLSI design space in terms of area/time efficiency is explored extensively for layered parallelism and pipelining with a Catapult C high-level-synthesis methodology.
Date Published: 2006-02-01

This item appears in the following Collection(s)

  • ECE Publications [1043 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • CMC Publications [275 items]
    Publications by Rice Faculty and graduate students in multimedia communications