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Configurable LDPC Decoder Architecture for Regular and Irregular Codes

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Title: Configurable LDPC Decoder Architecture for Regular and Irregular Codes
Author: Karkooti, Marjan; Radosavljevic, Predrag; Cavallaro, Joseph R.
Type: Journal article
Publisher: Springer
Citation: M. Karkooti, P. Radosavljevic and J. R. Cavallaro, "Configurable LDPC Decoder Architecture for Regular and Irregular Codes," Springer Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, vol. 53, no. 1-2, pp. 73-88, 2008.
Abstract: Low Density Parity Check (LDPC) codes are one of the best error correcting codes that enable the future generations of wireless devices to achieve higher data rates with excellent quality of service. This paper presents two novel flexible decoder architectures. The first one supports (3, 6) regular codes of rate 1/2 that can be used for different block lengths. The second decoder is more general and supports both regular and irregular LDPC codes with twelve combinations of code lengths −648, 1296, 1944-bits and code rates-1/2, 2/3, 3/4, 5/6- based on the IEEE 802.11n standard. All codes correspond to a block-structured parity check matrix, in which the sub-blocks are either a shifted identity matrix or a zero matrix. Prototype architectures for both LDPC decoders have been implemented and tested on a Xilinx field programmable gate array.
Date Published: 2008-11-01

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  • ECE Publications [1048 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • CMC Publications [275 items]
    Publications by Rice Faculty and graduate students in multimedia communications