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Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder

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dc.contributor.author Sun, Yang
Cavallaro, Joseph R.
dc.date.accessioned 2012-06-01T15:45:34Z
dc.date.available 2012-06-01T15:45:34Z
dc.date.issued 2011-09-01
dc.identifier.other http://scholar.google.com/scholar?cluster=17731176541114968406&hl=en&as_sdt=0,44
dc.identifier.uri http://hdl.handle.net/1911/64200
dc.description.abstract We present an efficient VLSI architecture for 3GPP LTE/LTE-Advance Turbo decoder by utilizing the algebraic-geometric properties of the quadratic permutation polynomial (QPP) interleaver. The high throughput 3GPP LTE/LTE-Advance Turbo codes require a highly-parallel decoder architecture. Turbo interleaver is known to be the main obstacle to the decoder parallelism due to the collisions it introduces in accesses to memory. The QPP interleaver solves the memory contention issues when several MAP decoders are used in parallel to improve Turbo decoding throughput. In this paper, we propose a low-complexity QPP interleaving address generator and a multi-bank memory architecture to enable parallel Turbo decoding. Design trade-offs in terms of area and throughput efficiency are placed an routed in a 65-nm CMOS technology with a core area of 8.3mm2 and a maximum clock frequency of 400 MHz. This parallel decoder, comprising 64 MAP decoder cores, can achieve a maximum decoding throughput of 1.28 Gbps at 6 iterations.
dc.description.sponsorship Nokia
dc.description.sponsorship Nokia Siemens Networks (NSN)
dc.description.sponsorship Xilinx
dc.description.sponsorship National Science Foundation
dc.publisher Elsevier
dc.subject QPP interleaver
Quadratic permutation polynomial
Turbo decoder
MAP decoder
VLSI
ASIC
3GPP LTE
dc.title Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder
dc.type Journal Paper
dc.citation.journalTitle Integration, the VLSI Journal
dc.contributor.center Center for Multimedia Communication
dc.citation.volumeNumber 44
dc.citation.pageNumber 305-315
dc.citation.issueNumber 4
dc.identifier.citation Y. Sun and J. R. Cavallaro, "Efficient hardware implementation of a highly-parallel 3GPP LTE/LTE-advance turbo decoder," Integration, the VLSI Journal, vol. 44, no. 4, pp. 305-315, 2011.

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    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
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    Publications by Rice Faculty and graduate students in multimedia communications