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Implementation of a High Throughput 3GPP Turbo Decoder on GPU

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dc.contributor.author Wu, Michael
Sun, Yang
Wang, Guohui
Cavallaro, Joseph R.
dc.date.accessioned 2012-06-01T14:59:19Z
dc.date.available 2012-06-01T14:59:19Z
dc.date.issued 2011-11-01
dc.identifier.issn 10.1007/s11265-011-0617-7
dc.identifier.other http://scholar.google.com/scholar?cluster=5352580959836314823&hl=en&as_sdt=0,44
dc.identifier.uri http://hdl.handle.net/1911/64198
dc.description.abstract Turbo code is a computationally intensive channel code that is widely used in current and upcoming wireless standards. General-purpose graphics processor unit (GPGPU) is a programmable commodity processor that achieves high performance computation power by using many simple cores. In this paper, we present a 3GPP LTE compliant Turbo decoder accelerator that takes advantage of the processing power of GPU to offer fast Turbo decoding throughput. Several techniques are used to improve the performance of the decoder. To fully utilize the computational resources on GPU, our decoder can decode multiple codewords simultaneously, divide the workload for a single codeword across multiple cores, and pack multiple codewords to fit the single instruction multiple data (SIMD) instruction width. In addition, we use shared memory judiciously to enable hundreds of concurrent multiple threads while keeping frequently used data local to keep memory access fast. To improve efficiency of the decoder in the high SNR regime, we also present a low complexity early termination scheme based on average extrinsic LLR statistics. Finally, we examine how different workload partitioning choices affect the error correction performance and the decoder throughput.
dc.description.sponsorship Renesas Mobile
dc.description.sponsorship Texas Instruments
dc.description.sponsorship Xilinx
dc.description.sponsorship National Science Foundation
dc.publisher Springer
dc.subject GPGPU
Turbo decoder
Accelerator
Parallel computing
Wireless
Error control codes
Turbo codes
dc.title Implementation of a High Throughput 3GPP Turbo Decoder on GPU
dc.type Journal Paper
dc.citation.journalTitle Journal of Signal Processing Systems
dc.contributor.center Center for Multimedia Communication
dc.citation.volumeNumber 65
dc.citation.pageNumber 171-183
dc.citation.issueNumber 2
dc.identifier.citation M. Wu, Y. Sun, G. Wang and J. R. Cavallaro, "Implementation of a High Throughput 3GPP Turbo Decoder on GPU," Journal of Signal Processing Systems, vol. 65, no. 2, pp. 171-183, 2011.

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  • ECE Publications [1082 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • CMC Publications [275 items]
    Publications by Rice Faculty and graduate students in multimedia communications