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Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations

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dc.contributor.author Sengupta, Chaitali
Cavallaro, Joseph R.
Wilson, William L.
Tittel, Frank K.
dc.date.accessioned 2012-05-30T18:11:34Z
dc.date.available 2012-05-30T18:11:34Z
dc.date.issued 1997-11-01
dc.identifier.other http://scholar.google.com/scholar?cluster=17094365680391327897&hl=en&as_sdt=0,44
dc.identifier.uri http://hdl.handle.net/1911/64196
dc.description.abstract In this paper, we address the problem of identifying and evaluating “critical features” in an integrated circuit (IC) layout. The “critical features” (e.g., nested elbows and open ends) are areas in the layout that are more prone to defects during photolithography. As feature sizes become smaller (sub-micron range) and as the chip area becomes larger, new process techniques (such as, using phase shifted masks for photolithography), are being used. Under these conditions, the only means to design compact circuits with good yield capabilities is to bring the design and process phases of IC manufacturing closer. This can be accomplished by integrating photolithography simulators with layout editors. However, evaluation of a large layout using a photolithography simulator is time consuming and often unnecessary. A much faster and efficient method would be to have a means of automatically identifying “critical features” in a layout and then evaluate the “critical features” using a photolithography simulator. Our technique has potential for use either to evaluate the limits of any new and nonconventional process technique in an early process definition phase or in a mask house, as a postprocessor to improve the printing capability of a given mask. This paper presents a CAD tool (an Integrated CAD Framework) which is built upon the layout editor, Magic, and the process simulator, Depict 3.0, that automatically identifies and evaluates “critical features”
dc.language.iso eng
dc.publisher IEEE
dc.subject Critical features
Photolithography
Process simulation
dc.title Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations
dc.type Journal Paper
dc.citation.journalTitle IEEE Transactions on Semiconductor Manufacturing
dc.contributor.center Center for Multimedia Communication
dc.citation.volumeNumber 10
dc.citation.pageNumber 482-494
dc.citation.issueNumber 4
dc.type.dcmi Text
dc.identifier.citation C. Sengupta, J. R. Cavallaro, W. L. Wilson and F. K. Tittel, "Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations," IEEE Transactions on Semiconductor Manufacturing, vol. 10, no. 4, pp. 482-494, 1997.

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  • ECE Publications [1046 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • CMC Publications [275 items]
    Publications by Rice Faculty and graduate students in multimedia communications