Fault-Tolerant VLSI Processor Array for the SVD

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Item Metadata Cavallaro, Joseph R.
Near, Christopher D.
Uyar, M. Umit 2012-05-18T19:30:49Z 2012-05-18T19:30:49Z 1989-10-01
dc.description.abstract Dynamic reconfiguration techniques are presented for a two-dimensional systolic array for the SVD of a matrix. Extra computation time is not required, since idle time inherent in the array is exploited. The scheme does not require additional spare processors and is easily implemented in VLSI. Only minor hardware and communication time increases within each processing element are required.
dc.description.sponsorship AT&T Bell Laboratories
dc.language.iso eng
dc.publisher IEEE Computer Society Press
dc.title Fault-Tolerant VLSI Processor Array for the SVD
dc.type Conference paper Center for Multimedia Communication
dc.citation.pageNumber 176-180
dc.citation.location Cambridge, MA
dc.citation.conferenceName IEEE International Conference on Computer Design: VLSI in Computers & Processors
dc.citation.conferenceDate 1989
dc.type.dcmi Text
dc.identifier.citation J. R. Cavallaro, C. D. Near and M. U. Uyar, "Fault-Tolerant VLSI Processor Array for the SVD," pp. 176-180, 1989.

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    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • CMC Publications [275 items]
    Publications by Rice Faculty and graduate students in multimedia communications