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Title:
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Fault-Tolerant VLSI Processor Array for the SVD |
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Author:
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Cavallaro, Joseph R.; Near, Christopher D.; Uyar, M. Umit
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Type:
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Conference Paper |
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Publisher:
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IEEE Computer Society Press |
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Citation:
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J. R. Cavallaro, C. D. Near and M. U. Uyar,"Fault-Tolerant VLSI Processor Array for the SVD," in IEEE International Conference on Computer Design: VLSI in Computers & Processors, 1989, pp. 176-180. |
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Abstract:
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Dynamic reconfiguration techniques are presented for a two-dimensional systolic array for the SVD of a matrix. Extra computation time is not required, since idle time inherent in the array is exploited. The scheme does not require additional spare processors and is easily implemented in VLSI. Only minor hardware and communication time increases within each processing element are required. |
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Date Published:
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1989-10-01 |
