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Fault-Tolerant VLSI Processor Array for the SVD

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Title: Fault-Tolerant VLSI Processor Array for the SVD
Author: Cavallaro, Joseph R.; Near, Christopher D.; Uyar, M. Umit
Type: Conference Paper
Publisher: IEEE Computer Society Press
Citation: J. R. Cavallaro, C. D. Near and M. U. Uyar,"Fault-Tolerant VLSI Processor Array for the SVD," in IEEE International Conference on Computer Design: VLSI in Computers & Processors, 1989, pp. 176-180.
Abstract: Dynamic reconfiguration techniques are presented for a two-dimensional systolic array for the SVD of a matrix. Extra computation time is not required, since idle time inherent in the array is exploited. The scheme does not require additional spare processors and is easily implemented in VLSI. Only minor hardware and communication time increases within each processing element are required.
Date Published: 1989-10-01

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  • ECE Publications [1034 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • CMC Publications [275 items]
    Publications by Rice Faculty and graduate students in multimedia communications