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Architectures for a CORDIC SVD Processor

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Title: Architectures for a CORDIC SVD Processor
Author: Cavallaro, Joseph R.; Luk, Franklin T.
Type: Conference Paper
Publisher: SPIE - The International Society for Optical Engineering
Citation: J. R. Cavallaro and F. T. Luk,"Architectures for a CORDIC SVD Processor," in Real Time Signal Processing IX, 1986, pp. 45-53.
Abstract: Architectures for systolic array processor elements for calculating the singular value decomposition (SVD) are proposed. These special purpose VLSI structures incorporate the coordinate rotation (CORDIC) algorithms to diagonalize 2X2 submatrices of a large array. The area-time complexity of the proposed architectures is analyzed along with topics related to a prototype implementation.
Date Published: 1986-08-21

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  • ECE Publications [1032 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students