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High Throughput VLSI Architecture for Soft-Output MIMO Detection Based on A Greedy Graph Algorithm

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Title: High Throughput VLSI Architecture for Soft-Output MIMO Detection Based on A Greedy Graph Algorithm
Author: Sun, Yang; Cavallaro, Joseph R.
Type: Conference paper
Publisher: ACM
Citation: Y. Sun and J. R. Cavallaro, "High Throughput VLSI Architecture for Soft-Output MIMO Detection Based on A Greedy Graph Algorithm," pp. 445-450, 2009.
Abstract: Maximum-likelihood (ML) decoding is a very computational- intensive task for multiple-input multiple-output (MIMO) wireless channel detection. This paper presents a new graph based algorithm to achieve near ML performance for soft MIMO detection. Instead of using the traditional tree search based structure, we represent the search space of the MIMO signals with a directed graph and a greedy algorithm is ap- plied to compute the a posteriori probability (APP) for each transmitted bit. The proposed detector has two advantages: 1) it keeps a fixed throughput and has a regular and parallel datapath structure which makes it amenable to high speed VLSI implementation, and 2) it attempts to maximize the a posteriori probability by making the locally optimum choice at each stage with the hope of finding the global minimum Euclidean distance for every transmitted bit x_k element of {-1, +1}. Compared to the soft K-best detector, the proposed solution significantly reduces the complexity because sorting is not required, while still maintaining good bit error rate (BER) performance. The proposed greedy detection algorithm has been designed and synthesized for a 4 x 4 16-QAM MIMO system in a TSMC 65 nm CMOS technology. The detector achieves a maximum throughput of 600 Mbps with a 0.79 mm2 core area.
Date Published: 2009-05-10

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  • ECE Publications [1048 items]
    Publications by Rice University Electrical and Computer Engineering faculty and graduate students
  • CMC Publications [275 items]
    Publications by Rice Faculty and graduate students in multimedia communications