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Y. Sun and J. R. Cavallaro, "A Flexible LDPC/Turbo Decoder Architecture," Journal of Signal Processing Systems, vol. 64, no. 1, pp. 1-16, 2011.
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Y. Sun and J. R. Cavallaro,"A LOW-POWER 1-Gbps RECONFIGURABLE LDPC DECODER DESIGN FOR MULTIPLE 4G WIRELESS STANDARDS," in IEEE International System-on-Chip (SOC) Conference, 2008, pp. 367-370.
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G. Wang, M. Wu, Y. Sun and J. R. Cavallaro,"A Massively Parallel Implementation of QC-LDPC Decoder on GPU," in IEEE 9th Symposium on Application Specific Processors (SASP), 2011, pp. 82-85.
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Y. Sun, G. Wang and J. R. Cavallaro,"Multi-Layer Parallel Decoding Algorithm and VLSI Architecture for Quasi-Cyclic LDPC Codes," in International Symposium on Circuits and Systems (ISCAS), 2011, pp. 1776-1779.
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Y. Sun, J. R. Cavallaro and T. Ly,"Scalable and Low Power LDPC Decoder Design Using High Level Algorithmic Synthesis," in IEEE International System-on-Chip (SOC) Conference, 2009, pp. 267-270.
Y. Sun and J. R. Cavallaro, "A Flexible LDPC/Turbo Decoder Architecture," Journal of Signal Processing Systems, vol. 64, no. 1, pp. 1-16, 2011.
Y. Sun and J. R. Cavallaro,"A LOW-POWER 1-Gbps RECONFIGURABLE LDPC DECODER DESIGN FOR MULTIPLE 4G WIRELESS STANDARDS," in IEEE International System-on-Chip (SOC) Conference, 2008, pp. 367-370.
G. Wang, M. Wu, Y. Sun and J. R. Cavallaro,"A Massively Parallel Implementation of QC-LDPC Decoder on GPU," in IEEE 9th Symposium on Application Specific Processors (SASP), 2011, pp. 82-85.
Y. Sun, G. Wang and J. R. Cavallaro,"Multi-Layer Parallel Decoding Algorithm and VLSI Architecture for Quasi-Cyclic LDPC Codes," in International Symposium on Circuits and Systems (ISCAS), 2011, pp. 1776-1779.
Y. Sun, J. R. Cavallaro and T. Ly,"Scalable and Low Power LDPC Decoder Design Using High Level Algorithmic Synthesis," in IEEE International System-on-Chip (SOC) Conference, 2009, pp. 267-270.