Browse this collection by:
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Y. Guo, "Advanced MIMO-CDMA Receiver for Interference Suppression: Algorithms, System-on-Chip Architectures and Design Methodology," Ph.D. Thesis, 2005.
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A. Sendonaris, "Advanced Techniques for Next-Generation Wireless Systems," Ph.D. Thesis, 1999.
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R. Madyastha, "Antenna Arrays for Wireless CDMA Communication Systems," Ph.D. Thesis, 1997.
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A. Khoshnevis, "Coding-Spreading Tradeoff for Lattice Codes," Masters Thesis, 2001.
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Y. Guo, J. (. Zhang, D. McCain and J. R. Cavallaro,"Displacement MIMO Kalman Equalizer for CDMA Downlink in Fast Fading Channels," in IEEE Globecom,
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Y. Guo, D. McCain and J. R. Cavallaro,"FFT-Accelerated Iterative MIMO Chip Equalizer Architecture For CDMA Downlink," in IEEE International Conference on Acoustics, Speech, and Signal Processing (ICASSP),
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Y. Guo, D. McCain and J. R. Cavallaro,"Hermitian Optimization and Scalable VLSI Architecture for Circulant Approximated MIMO Equalizer in CDMA Downlink," in IEEE Vehicular Technology Conference (VTC),
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Y. Guo and J. R. Cavallaro, "A low complexity and low power SoC design architecture for adaptive MAI suppression in CDMA systems," Journal of VLSI Signal Processing, 2005.
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Y. Guo, D. McCain and J. R. Cavallaro,"Low Complexity System-On-Chip Architectures Of Optimal Parallel-Residue-Compensation In CDMA Systems," in IEEE International Symposium on Circuits and Systems (ISCAS),, pp. 77-80.
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S. Das, "Multiuser Information Processing in Wireless Communication," Ph.D. Thesis, 2000.
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C. Sengupta, J. R. Cavallaro and B. Aazhang, "On Multipath Channel Estimation for CDMA Systems Using Multiple Sensors," IEEE Transactions on Communications, vol. 49, no. 3, pp. 543-553, 2001.
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V. Chandrasekhar, "Reducing Dynamic Power Consumption in Next Generation DS-CDMA Mobile Communication Receivers," Masters Thesis, 2002.
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Y. Guo, "Resource Allocation in Wireless CDMA Multimedia Networks," Ph.D. Thesis, 1999.
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S. Bhashyam, "Signal and Information Processing for Wireless Communication Systems," Ph.D. Thesis, 2001.
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Y. Guo, D. McCain and J. R. Cavallaro, "Structured Iterative and Circulant MIMO Chip Equalizer Architectures with FFT-acceleration for CDMA Systems," IEEE Transaction on Vehicular Technology, 2005.
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G. Xu, S. Rajagopal, J. R. Cavallaro and B. Aazhang, "VLSI implementation of the multistage detector for next generation wideband CDMA receivers," Journal of VLSI Signal Processing, vol. 30, no. 1-3, pp. 21-33, 2002.