Browse this collection by:
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S. Rajagopal, B. A. Jones and J. R. Cavallaro,"Task Partitioning Wireless Base-station Receiver Algorithms on Multiple DSPs and FPGAs," in International Conference on Signal Processing Applications and Technology (ICSPAT),
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M. L. Leuschen, J. R. Cavallaro and I. D. Walker,"Testing on the Curve: Nonlinear Analytical Redundancy for Fault Detection," in Ninth ANS Topical Meeting on Robotics and Remote Systems, 2001, pp. Session 22, Paper F131.
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S. Bhashyam, A. M. Sayeed and B. Aazhang, "Time-Selective Signaling and Reception for Communication over Multipath Fading Channels," IEEE Transactions on Communications, vol. 48, no. 1, pp. 83-94, 2000.
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R. H. Riedi and W. Willinger, "Toward an Improved Understanding of Network Traffic Dynamics," Self-similar Network Traffic and Performance Evaluation, eds Park and Willinger, Wiley, pp. 507-530, 2000.
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Y. Sun and J. R. Cavallaro, "Trellis-Search Based Soft-Input Soft-Output MIMO Detector: Algorithm and VLSI Architecture," IEEE Transactions on Signal Processing, vol. 60, no. 5, pp. 2617-2627, 2012.
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S. Rajagopal and J. R. Cavallaro, "Truncated on-line arithmetic with applications to communication systems," IEEE Transactions on Computers, vol. 55, no. 10, pp. 1240-1252, 2006.
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S. Rajagopal and J. R. Cavallaro, "Truncated Online Arithmetic with Applications to Communication Systems," 2006.
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F. K. Tittel, M. Erdelyi, C. Sengupta, Z. Bor, G. Szabo, J. R. Cavallaro, M. C. Smayling and W. L. Wilson,"Ultrahigh Resolution Lithography with Excimer Lasers," in NATO Workshop on Gas Lasers - Recent Developments and Future Prospects, 1995, pp. 263-272.
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Y. Sun and J. R. Cavallaro,"UNIFIED DECODER ARCHITECTURE FOR LDPC/TURBO CODES," in IEEE Workshop on Signal Processing Systems (SIPS), 2008, pp. 13-18.
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Y. Guo and D. McCain,"Untimed-C based SoC Architecture Design Space Exploration for 3G and Beyond Wireless Systems," in Design and Verification Conference,
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I. D. Walker and J. R. Cavallaro,"The Use of Fault Trees for the Design of Robots for Hazardous Environments," in IEEE Annual Reliability and Maintainability Symposium, 1996, pp. 229-235.
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A. Chakrabarti, A. Sabharwal and B. Aazhang,"Using Predictable Observer Mobility for Power Efficient Design of Sensor Networks," in Information Processing in Sensor Networks,
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J. R. Cavallaro,"VLSI Architectures and Rapid Prototyping Testbeds for Wireless Systems," in International Workshop on Convergent Technologies (IWCT), 2005
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J. R. Cavallaro,"VLSI Architectures for Multitier Wireless Systems," in Air Force Research Lab Collaborative Technologies Workshop,, pp. 28-31.
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Y. Sun, M. Karkooti and J. R. Cavallaro,"VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes," in IEEE International Symposium on Circuits and Systems (ISCAS), 2007, pp. 2104-2107.
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G. Xu, S. Rajagopal, J. R. Cavallaro and B. Aazhang, "VLSI implementation of the multistage detector for next generation wideband CDMA receivers," Journal of VLSI Signal Processing, vol. 30, no. 1-3, pp. 21-33, 2002.
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B. A. Jones, "W-CDMA real-time algorithm implementation and evaluation," ELEC 599 Project Report, 2000.
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K. Amiri, Y. Sun, P. Murphy, C. Hunter, J. R. Cavallaro and A. Sabharwal,"WARP, a Modular Testbed for Configurable Wireless Network Research at Rice," in IEEE Galveston Bay Section Symposium for Space Applications of Wireless and RFID, 2007
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K. Amiri, Y. Sun, P. Murphy, C. Hunter, J. R. Cavallaro and A. Sabharwal,"WARP, a UnifiedWireless Network Testbed for Education and Research," in IEEE International Conference on Microelectronic Systems Education (MSE), 2007, pp. 53-54.
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J. Feinsmith, J. H. Aylor, R. Hodson, B. Courtois, J. R. Cavallaro, J. Hines, C. Pina, M. Smith and D. Bouldin, "What's Next for Microelectronics Education - Editorial," IEEE Design and Test of Computers, vol. 14, no. 4, pp. 95-102, 1997.
S. Rajagopal, B. A. Jones and J. R. Cavallaro,"Task Partitioning Wireless Base-station Receiver Algorithms on Multiple DSPs and FPGAs," in International Conference on Signal Processing Applications and Technology (ICSPAT),
M. L. Leuschen, J. R. Cavallaro and I. D. Walker,"Testing on the Curve: Nonlinear Analytical Redundancy for Fault Detection," in Ninth ANS Topical Meeting on Robotics and Remote Systems, 2001, pp. Session 22, Paper F131.
S. Bhashyam, A. M. Sayeed and B. Aazhang, "Time-Selective Signaling and Reception for Communication over Multipath Fading Channels," IEEE Transactions on Communications, vol. 48, no. 1, pp. 83-94, 2000.
R. H. Riedi and W. Willinger, "Toward an Improved Understanding of Network Traffic Dynamics," Self-similar Network Traffic and Performance Evaluation, eds Park and Willinger, Wiley, pp. 507-530, 2000.
Y. Sun and J. R. Cavallaro, "Trellis-Search Based Soft-Input Soft-Output MIMO Detector: Algorithm and VLSI Architecture," IEEE Transactions on Signal Processing, vol. 60, no. 5, pp. 2617-2627, 2012.
S. Rajagopal and J. R. Cavallaro, "Truncated on-line arithmetic with applications to communication systems," IEEE Transactions on Computers, vol. 55, no. 10, pp. 1240-1252, 2006.
S. Rajagopal and J. R. Cavallaro, "Truncated Online Arithmetic with Applications to Communication Systems," 2006.
F. K. Tittel, M. Erdelyi, C. Sengupta, Z. Bor, G. Szabo, J. R. Cavallaro, M. C. Smayling and W. L. Wilson,"Ultrahigh Resolution Lithography with Excimer Lasers," in NATO Workshop on Gas Lasers - Recent Developments and Future Prospects, 1995, pp. 263-272.
Y. Sun and J. R. Cavallaro,"UNIFIED DECODER ARCHITECTURE FOR LDPC/TURBO CODES," in IEEE Workshop on Signal Processing Systems (SIPS), 2008, pp. 13-18.
Y. Guo and D. McCain,"Untimed-C based SoC Architecture Design Space Exploration for 3G and Beyond Wireless Systems," in Design and Verification Conference,
I. D. Walker and J. R. Cavallaro,"The Use of Fault Trees for the Design of Robots for Hazardous Environments," in IEEE Annual Reliability and Maintainability Symposium, 1996, pp. 229-235.
A. Chakrabarti, A. Sabharwal and B. Aazhang,"Using Predictable Observer Mobility for Power Efficient Design of Sensor Networks," in Information Processing in Sensor Networks,
J. R. Cavallaro,"VLSI Architectures and Rapid Prototyping Testbeds for Wireless Systems," in International Workshop on Convergent Technologies (IWCT), 2005
J. R. Cavallaro,"VLSI Architectures for Multitier Wireless Systems," in Air Force Research Lab Collaborative Technologies Workshop,, pp. 28-31.
Y. Sun, M. Karkooti and J. R. Cavallaro,"VLSI Decoder Architecture for High Throughput, Variable Block-size and Multi-rate LDPC Codes," in IEEE International Symposium on Circuits and Systems (ISCAS), 2007, pp. 2104-2107.
G. Xu, S. Rajagopal, J. R. Cavallaro and B. Aazhang, "VLSI implementation of the multistage detector for next generation wideband CDMA receivers," Journal of VLSI Signal Processing, vol. 30, no. 1-3, pp. 21-33, 2002.
B. A. Jones, "W-CDMA real-time algorithm implementation and evaluation," ELEC 599 Project Report, 2000.
K. Amiri, Y. Sun, P. Murphy, C. Hunter, J. R. Cavallaro and A. Sabharwal,"WARP, a Modular Testbed for Configurable Wireless Network Research at Rice," in IEEE Galveston Bay Section Symposium for Space Applications of Wireless and RFID, 2007
K. Amiri, Y. Sun, P. Murphy, C. Hunter, J. R. Cavallaro and A. Sabharwal,"WARP, a UnifiedWireless Network Testbed for Education and Research," in IEEE International Conference on Microelectronic Systems Education (MSE), 2007, pp. 53-54.
J. Feinsmith, J. H. Aylor, R. Hodson, B. Courtois, J. R. Cavallaro, J. Hines, C. Pina, M. Smith and D. Bouldin, "What's Next for Microelectronics Education - Editorial," IEEE Design and Test of Computers, vol. 14, no. 4, pp. 95-102, 1997.