Browse this collection by:
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S. Rajagopal, "Baseband Architecture Design for Future Wireless Base-Station Receivers," Masters Thesis, 2000.
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S. Rajagopal and J. R. Cavallaro,"A bit-streaming pipelined multiuser detector for wireless communications," in IEEE International Symposium on Circuits and Systems (ISCAS),, pp. 128-131.
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A. Khoshnevis, "Coding-Spreading Tradeoff for Lattice Codes," Masters Thesis, 2001.
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S. Rajagopal and J. R. Cavallaro, "Communication Processors," Wiley Encyclopedia of Computer Science and Engineering, 2005.
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Y. Guo and D. McCain,"Compact Hardware Accelerator for Functional Verification and Rapid Prototyping of 4G Wireless Communication Systems," in Asilomar Conference on Signals, Systems, and Computers,
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M. Myllylä, P. Silvola, M. Juntti and J. R. Cavallaro,"COMPARISON OF TWO NOVEL LIST SPHERE DETECTOR ALGORITHMS FOR MIMO-OFDM SYSTEMS," in IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC), 2006
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M. C. Brogioli and J. R. Cavallaro,"Compiler Driven Architecture Design Space Exploration for DSP Workloads: A Study in Software Programmability Versus Hardware Acceleration," in 43rd Asilomar Conference on Signals, Systems and Computers, 2009, pp. 221-225.
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M. Myllylä, J. Hintikka, J. R. Cavallaro, M. Juntti, M. Limingoja and A. Byman,"Complexity Analysis of MMSE Detector Architectures for MIMO OFDM Systems," in 39th Asilomar Conference on Signals, Systems and Computers, 2005, pp. 75-81.
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Y. Sun, Y. Zhu, M. Goel and J. R. Cavallaro,"Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4GWireless Standards," in IEEE International Conference on Application-Specific System, Architectures and Processors (ASAP), 2008, pp. 209-214.
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Y. Sun, J. R. Cavallaro, Y. Zhu and G. Manish, "Configurable and Scalable Turbo Decoder for 4G Wireless Receivers," vol. 2010, pp. 622-643, 2010.
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M. Karkooti, P. Radosavljevic and J. R. Cavallaro, "Configurable LDPC Decoder Architecture for Regular and Irregular Codes," Springer Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, vol. 53, no. 1-2, pp. 73-88, 2008.
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K. Amiri, M. Wu, J. R. Cavallaro and J. Lilleberg, "Cooperative Partial Detection Using MIMO Relays," IEEE Transactions on Signal Processing, vol. 59, no. 10, pp. 5039-5049, 2011.
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J. R. Cavallaro and F. T. Luk, "CORDIC Arithmetic for an SVD Processor," Journal of Parallel and Distributed Computing, vol. 5, no. 3, pp. 271-290, 1988.
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J. R. Cavallaro and F. T. Luk,"CORDIC Arithmetic for an SVD Processor," in IEEE 8th Symposium on Computer Arithmetic, 1987, pp. 113-120.
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A. Chakrabarti, A. Sabharwal and B. Aazhang, "Data Collection by a Mobile Observer in a Single-hop Sensor Network," ACM Transactions on Sensor Networks, 2005.
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S. Rajagopal, "Data-parallel Digital Signal Processors: Algorithm Mapping, Architecture Scaling and Workload Adaptation," Ph.D. Thesis, 2004.
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D. Rajan, A. Sabharwal and B. Aazhang,"Delay and Rate Constrained Transmission Policies over Wireless Channels," in Communication Theory Mini-Conference in conjunction with GLOBECOM,
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M. Khojastepour and A. Sabharwal,"Delay-constrained Scheduling: Power Efficiency, Filter Design, and Bounds," in IEEE INFOCOM,
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M. C. Brogioli, M. Gadhiok and J. R. Cavallaro,"Design and Analysis of Heterogeneous DSP/FPGA Based Architectures for 3GPP Wireless Systems," in IEEE Real-Time and Embedded Technology and Applications Symposium; Work in Progress Session, 2006, pp. 29-32.
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C. Dick, K. Amiri, J. R. Cavallaro and R. Rao,"Design and Architecture of Spatial Multiplexing MIMO Decoders for FPGAs," in 42nd Asilomar Conference on Signals, Systems and Computers, 2008, pp. 160-164.
S. Rajagopal, "Baseband Architecture Design for Future Wireless Base-Station Receivers," Masters Thesis, 2000.
S. Rajagopal and J. R. Cavallaro,"A bit-streaming pipelined multiuser detector for wireless communications," in IEEE International Symposium on Circuits and Systems (ISCAS),, pp. 128-131.
A. Khoshnevis, "Coding-Spreading Tradeoff for Lattice Codes," Masters Thesis, 2001.
S. Rajagopal and J. R. Cavallaro, "Communication Processors," Wiley Encyclopedia of Computer Science and Engineering, 2005.
Y. Guo and D. McCain,"Compact Hardware Accelerator for Functional Verification and Rapid Prototyping of 4G Wireless Communication Systems," in Asilomar Conference on Signals, Systems, and Computers,
M. Myllylä, P. Silvola, M. Juntti and J. R. Cavallaro,"COMPARISON OF TWO NOVEL LIST SPHERE DETECTOR ALGORITHMS FOR MIMO-OFDM SYSTEMS," in IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC), 2006
M. C. Brogioli and J. R. Cavallaro,"Compiler Driven Architecture Design Space Exploration for DSP Workloads: A Study in Software Programmability Versus Hardware Acceleration," in 43rd Asilomar Conference on Signals, Systems and Computers, 2009, pp. 221-225.
M. Myllylä, J. Hintikka, J. R. Cavallaro, M. Juntti, M. Limingoja and A. Byman,"Complexity Analysis of MMSE Detector Architectures for MIMO OFDM Systems," in 39th Asilomar Conference on Signals, Systems and Computers, 2005, pp. 75-81.
Y. Sun, Y. Zhu, M. Goel and J. R. Cavallaro,"Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4GWireless Standards," in IEEE International Conference on Application-Specific System, Architectures and Processors (ASAP), 2008, pp. 209-214.
Y. Sun, J. R. Cavallaro, Y. Zhu and G. Manish, "Configurable and Scalable Turbo Decoder for 4G Wireless Receivers," vol. 2010, pp. 622-643, 2010.
M. Karkooti, P. Radosavljevic and J. R. Cavallaro, "Configurable LDPC Decoder Architecture for Regular and Irregular Codes," Springer Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, vol. 53, no. 1-2, pp. 73-88, 2008.
K. Amiri, M. Wu, J. R. Cavallaro and J. Lilleberg, "Cooperative Partial Detection Using MIMO Relays," IEEE Transactions on Signal Processing, vol. 59, no. 10, pp. 5039-5049, 2011.
J. R. Cavallaro and F. T. Luk, "CORDIC Arithmetic for an SVD Processor," Journal of Parallel and Distributed Computing, vol. 5, no. 3, pp. 271-290, 1988.
J. R. Cavallaro and F. T. Luk,"CORDIC Arithmetic for an SVD Processor," in IEEE 8th Symposium on Computer Arithmetic, 1987, pp. 113-120.
A. Chakrabarti, A. Sabharwal and B. Aazhang, "Data Collection by a Mobile Observer in a Single-hop Sensor Network," ACM Transactions on Sensor Networks, 2005.
S. Rajagopal, "Data-parallel Digital Signal Processors: Algorithm Mapping, Architecture Scaling and Workload Adaptation," Ph.D. Thesis, 2004.
D. Rajan, A. Sabharwal and B. Aazhang,"Delay and Rate Constrained Transmission Policies over Wireless Channels," in Communication Theory Mini-Conference in conjunction with GLOBECOM,
M. Khojastepour and A. Sabharwal,"Delay-constrained Scheduling: Power Efficiency, Filter Design, and Bounds," in IEEE INFOCOM,
M. C. Brogioli, M. Gadhiok and J. R. Cavallaro,"Design and Analysis of Heterogeneous DSP/FPGA Based Architectures for 3GPP Wireless Systems," in IEEE Real-Time and Embedded Technology and Applications Symposium; Work in Progress Session, 2006, pp. 29-32.
C. Dick, K. Amiri, J. R. Cavallaro and R. Rao,"Design and Architecture of Spatial Multiplexing MIMO Decoders for FPGAs," in 42nd Asilomar Conference on Signals, Systems and Computers, 2008, pp. 160-164.