Now showing items 14-33 of 272
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O. Gustafsson, K. Amiri, D. Andersson, A. Blad, C. Bonner, J. R. Cavallaro, J. Declerck, A. Dejonghe, P. Eliardsson, M. Glasse, A. Hayar, L. Hollevoet, C. Hunter, M. Joshi, F. Kaltenberger, R. Knopp, K. Le, Z. Miljanic, P. Murphy, F. Naessens, N. Nikaein, D. Nussbaum, R. Pacalet, P. Raghavan, A. Sabharwal, O. Sarode, P. Spasojevic, Y. Sun, H. M. Tullberg, T. Vander Aa, L. Van der Perre, M. Wetterwald and M. Wu,"Architectures for Cognitive Radio Testbeds and Demonstrators – An Overview," in Cognitive Radio Oriented Wireless Networks & Communications (CROWNCOM), 2010, pp. 1-6. -
J. R. Cavallaro, "Architectures for Heterogeneous Multi-Tier Networks," Kluwer Journal on Wireless Personal Communications, 2002. -
S. Das, S. Rajagopal, C. Sengupta and J. R. Cavallaro,"Arithmetic Acceleration Techniques for Wireless Communication Receivers," in Asilomar Conference on Signals, Systems, and Computers,, pp. 1469 - 1474. -
J. Ketonen, M. Myllylä, M. Juntti and J. R. Cavallaro,"ASIC Implementation Comparison of SIC and LSD Receivers for MIMO-OFDM," in 42nd Asilomar Conference on Signals, Systems and Computers, 2008, pp. 1881-1885. -
J. R. Cavallaro, C. Sengupta, F. K. Tittel and W. L. J. Wilson,"Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations," in NSF Design and Manufacturing Grantees Conference, 1996, pp. 345-346. -
C. Sengupta, J. R. Cavallaro, W. L. Wilson and F. K. Tittel, "Automated Evaluation of Critical Features in VLSI Layouts Based on Photolithographic Simulations," IEEE Transactions on Semiconductor Manufacturing, vol. 10, no. 4, pp. 482-494, 1997. -
S. Rajagopal, "Baseband Architecture Design for Future Wireless Base-Station Receivers," Masters Thesis, 2000. -
S. Rajagopal and J. R. Cavallaro,"A bit-streaming pipelined multiuser detector for wireless communications," in IEEE International Symposium on Circuits and Systems (ISCAS),, pp. 128-131. -
A. Khoshnevis, "Coding-Spreading Tradeoff for Lattice Codes," Masters Thesis, 2001. -
S. Rajagopal and J. R. Cavallaro, "Communication Processors," Wiley Encyclopedia of Computer Science and Engineering, 2005. -
Y. Guo and D. McCain,"Compact Hardware Accelerator for Functional Verification and Rapid Prototyping of 4G Wireless Communication Systems," in Asilomar Conference on Signals, Systems, and Computers, -
M. Myllylä, P. Silvola, M. Juntti and J. R. Cavallaro,"COMPARISON OF TWO NOVEL LIST SPHERE DETECTOR ALGORITHMS FOR MIMO-OFDM SYSTEMS," in IEEE International Symposium on Personal, Indoor and Mobile Radio Communications (PIMRC), 2006 -
M. C. Brogioli and J. R. Cavallaro,"Compiler Driven Architecture Design Space Exploration for DSP Workloads: A Study in Software Programmability Versus Hardware Acceleration," in 43rd Asilomar Conference on Signals, Systems and Computers, 2009, pp. 221-225. -
M. Myllylä, J. Hintikka, J. R. Cavallaro, M. Juntti, M. Limingoja and A. Byman,"Complexity Analysis of MMSE Detector Architectures for MIMO OFDM Systems," in 39th Asilomar Conference on Signals, Systems and Computers, 2005, pp. 75-81. -
Y. Sun, Y. Zhu, M. Goel and J. R. Cavallaro,"Configurable and Scalable High Throughput Turbo Decoder Architecture for Multiple 4GWireless Standards," in IEEE International Conference on Application-Specific System, Architectures and Processors (ASAP), 2008, pp. 209-214. -
Y. Sun, J. R. Cavallaro, Y. Zhu and G. Manish, "Configurable and Scalable Turbo Decoder for 4G Wireless Receivers," vol. 2010, pp. 622-643, 2010. -
M. Karkooti, P. Radosavljevic and J. R. Cavallaro, "Configurable LDPC Decoder Architecture for Regular and Irregular Codes," Springer Journal of VLSI Signal Processing Systems for Signal, Image and Video Technology, vol. 53, no. 1-2, pp. 73-88, 2008. -
K. Amiri, M. Wu, J. R. Cavallaro and J. Lilleberg, "Cooperative Partial Detection Using MIMO Relays," IEEE Transactions on Signal Processing, vol. 59, no. 10, pp. 5039-5049, 2011. -
J. R. Cavallaro and F. T. Luk, "CORDIC Arithmetic for an SVD Processor," Journal of Parallel and Distributed Computing, vol. 5, no. 3, pp. 271-290, 1988. -
J. R. Cavallaro and F. T. Luk,"CORDIC Arithmetic for an SVD Processor," in IEEE 8th Symposium on Computer Arithmetic, 1987, pp. 113-120.